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Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class

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Abstract

In this paper we propose an architecture design methodology to optimize the throughput of MD4-based hash algorithms. The proposed methodology includes an iteration bound analysis of hash algorithms, which is the theoretical delay limit, and Data Flow Graph transformations to achieve the iteration bound. We applied the methodology to some MD4-based hash algorithms such as SHA1, MD5 and RIPEMD-160. Since SHA1 is the algorithm which requires all the techniques we show, we also synthesized the transformed SHA1 algorithm in a 0.18 μm CMOS technology in order to verify its correctness and its achievement of high throughput. To the best of our knowledge, the proposed SHA1 architecture is the first to achieve the theoretical throughput optimum beating all previously published results. Though we demonstrate a limited number of examples, this design methodology can be applied to any other MD4-based hash algorithm.

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Acknowledgements

This work is supported by NSF CCF-0541472, SRC, FWO and funds from Katholieke Universiteit Leuven.

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Authors and Affiliations

  1. Electrical Engineering, University of California, Los Angeles, 56-125B Engineering IV Building, 420 Westwood Plaza, Los Angeles, CA, 90095-1594, USA

    Yong Ki Lee, Herwin Chan & Ingrid Verbauwhede

  2. Katholieke Universiteit Leuven, Leuven, Belgium

    Ingrid Verbauwhede

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  1. Yong Ki Lee
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  2. Herwin Chan
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  3. Ingrid Verbauwhede
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Correspondence to Yong Ki Lee.

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Lee, Y.K., Chan, H. & Verbauwhede, I. Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class. J Sign Process Syst Sign Image Video Technol 53, 89–102 (2008). https://doi.org/10.1007/s11265-008-0168-8

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