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A low-cost and latency bypass channel-based on-chip network

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Abstract

The number of cores on the chip increases rapidly; therefore, scalability is the most important design choice. Mesh-based Networks-on-Chip (NoC) are the most widely used topologies as a scalable alternative for traditional shared bus in many-core chips today. As the NoCs diameter increases, the low-latency communication between cores is becoming more important to ensure sustained scalability, and higher performance. In the ideal network, the low-load network latency between a source and destination is almost equal to single cycle. In this work, we propose a router for network-on-chip called Bypass router that leads to create a single-cycle data path all the way from the source to the destination. We do not use any additional control links in the network; instead the proposed router is compatible with all topologies and deterministic routing algorithm. We also propose a new routing algorithm to use the advantages of our router design. The area consumption is also reduced on \( 4\times 4, 8\times 8, 16\times 16 \) mesh topologies, compared to SMART network (Krishna et al. IEEE 19th international symposium on high performance computer architecture (HPCA2013), 2013). System simulations with Noxim simulators demonstrate at mean 60 % reduction in latencies across synthetic traffic patterns compared to a baseline router.

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Correspondence to Amir Fadakar Noghondar.

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Fadakar Noghondar, A., Reshadi, M. A low-cost and latency bypass channel-based on-chip network. J Supercomput 71, 3770–3786 (2015). https://doi.org/10.1007/s11227-015-1466-0

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  • DOI: https://doi.org/10.1007/s11227-015-1466-0

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