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Link Testing: a Survey of Current Trends in Network on Chip

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Abstract

As an excellent interconnection model, Network on chip (NoC) addresses different on-chip communication problems and can meet different requirements of performance, cost and reliability. Currently, with the growth of technology practice, wire-based interconnections are more and more unreliable. Consequently, growing sources of unreliability directly impact upon both signals and wires leading to some kinds of while misbehaviors in wires called faults. The literature offers various mechanisms designed for detection and diagnosis of such faults. However, this current paper aims to comprehensively survey these various state of art mechanisms of designed for detection and diagnosis of such faults and discusses them in detail in a way that is quite novel, not found in the previous publications. This is the pioneering survey paper which is concerned with classifying link testing approaches in two Online and Offline categories and extracts some conceptualizations to assist the research community. Besides making comparison among various link testing mechanisms on different parameters in the typical comparative table, detailed explanations are also presented about these parameters in NoC architecture.

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Authors and Affiliations

  1. Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

    Babak Aghaei & Midia Reshadi

  2. Iran Telecommunication Research Center, ITRC, Tehran, Iran

    Ahmad Khademzadeh & Kambiz Badie

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  3. Midia Reshadi
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  4. Kambiz Badie
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Correspondence to Kambiz Badie.

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Responsible Editor: S. T. Chakradhar

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Aghaei, B., Khademzadeh, A., Reshadi, M. et al. Link Testing: a Survey of Current Trends in Network on Chip. J Electron Test 33, 209–225 (2017). https://doi.org/10.1007/s10836-017-5646-0

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  • DOI: https://doi.org/10.1007/s10836-017-5646-0

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