Abstract
In this paper, a new on-chip signal generator for charge-based capacitance measurement (CBCM) circuit is proposed. As compared to conventional circuits that use two input off-chip clock signals or on-chip delay cells, the proposed circuit uses an I/Q splitter and an AND function to obtain 1/2 and 1/8 duty cycle signals, hence reduces the potential mismatch between these two clock signals. The proposed circuit makes it possible to use higher input frequency in measurement. As a result, smaller capacitance can be measured using the same measurement facilities without the loss of accuracy. Implemented in a standard 180 nm CMOS process, the proposed signal generator only occupies 40 μm × 18 μm while consuming less than 60 μW at an input frequency of 100 MHz. Simulation and measurement results suggest that the CBCM measuring circuits with proposed signal generator achieves the same accuracy as compared to conventional circuits while the requirement of measurement facilities can be considerably relaxed.
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References
Cao SH, Yu XP, Pan Y, Shi Z, Hu CH (2012) Considerations and optimization of measurement accuracy of capacitance in nano-scale CMOS technology. Nanosci Nanotechnol Lett 4(9):924–929
Chang YW, Chang HW, Hsieh CH et al (2004) A novel simple CBCM method free from charge injection-induced errors. Electron Device Lett 25(5):262–264
Chang YW, Chang HW, Lu CY, King YC, Ting W, Ku YH (2006) Interconnect capacitance characterization using charge-injection-induced error-free (CIEF) charge-based capacitance measurement (CBCM). IEEE Trans Semicond Manuf 19(1):50–56
Chang YW, Chang HW, Lu CY, King YC, Chen KC (2008) Combining a novel charge-based capacitance measurement (CBCM) technique and split–method to specifically characterize the STI stress effect along the width direction of MOSFET devices. IEEE Electron Device Lett 29(6):641–644
Chen JC, McGaughy BW, Sylvester D, Hu C (1996) An on-chip, attofarad interconnect charge-based capacitance measurement (CBCM) technique. Proc IEEE Int Electron Devices Meet (IEDM) 69–72
Huang XL, Huang JL, Chen HI, Chen CY, Kuo-Tsai T, Huang MF, Kwai DM (2012) An MCT-based bit-weight extraction technique for embedded SAR ADC testing and calibration. J Electron Test 28(5):705–722
Huang XL, Kang PY, Yu YC, Huang JL (2011) Histogram-based calibration of capacitor mismatch and comparator offset for 1-bit/stage pipelined ADCs. J Electron Test 27(4):441–453
Ning Z, Delecourt HX, De Schepper L, Gillon R, Tack M (2005) Precise analogue characterization of MIM capacitors using an improved charge-based capacitance measurement (CBCM) technique. Proc 35th IEEE European Solid-State Device Research Conference (ESSDERC) 269–272
Sylvester D, Chen JC, Hu C (1998) Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation. IEEE J Solid State Circuits 33(3):449–453
Acknowledgments
This work was supported by National Science Foundation China (grant 61106034 and 61274034) and Natural Science Foundation of Jiangsu Province of China under Grant Number BK2012644.
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Responsible Editor: K. K. Saluja
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Yu, X.P., Tian, R.Q., Xu, W.L. et al. A New On-chip Signal Generator for Charge-Based Capacitance Measurement Circuit. J Electron Test 31, 329–333 (2015). https://doi.org/10.1007/s10836-015-5526-4
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DOI: https://doi.org/10.1007/s10836-015-5526-4