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A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design

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Abstract

The goal of this work is to develop a methodical approach for analytical soft error sensitivity analysis in SRAM-based FPGAs. Compared to other non-destructive techniques, the proposed approach can be applied very early in a design flow. This is achieved by extracting information about an application under development from high level models (e.g. C/C++ descriptions or Matlab Simulink models) and then invoking pre-established libraries where other information related to soft error sensitivity of primitive components are stored beforehand. Our library-based approach is validated by comparing our early estimation results to those obtained through synthesis, placement and routing of complete designs, for two different ways of estimating the number of potentially critical configuration bits. We first explore two different design architectures for implementing Finite Impulse Response filters. The design architectures are explored under two different implementation options, for a Xilinx Virtex-5 FPGA: LUT based and DSP48E block based. Then we apply our estimation technique on a more complex design. namely a GMSK demodulator. Results show that the worst case relative error, caused by our estimation technique with respect to the results obtained after synthesis, placement and routing is 7,2 %, and in most cases, it is less than 5 %. Mean time between failures are provided for the different design architecture and implementation options, to illustrate how our technique can help designers make early choices to build more reliable designs without performing the whole implementation, as our early estimation results are close to those obtained later in the design process.

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Authors and Affiliations

  1. Electrical Eng. Department, Ecole de technologie superieure, Montreal, QC, Canada

    C. Thibeault, C. Hobeika & F. Z. Tazi

  2. CMC Microsystems, Kingston, ON, Canada

    Y. Hariri

  3. Electrical Eng. Department, Ecole Polytechnique de Montreal, Montreal, QC, Canada

    S. R. Hasan, Y. Savaria & Y. Audet

Authors
  1. C. Thibeault
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  2. Y. Hariri
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  3. S. R. Hasan
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  4. C. Hobeika
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  5. Y. Savaria
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  6. Y. Audet
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  7. F. Z. Tazi
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Correspondence to C. Thibeault.

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Responsible Editor: M. Violante

Appendix

Appendix

The XDL file is broadly divided into two sections: the instance section and the interconnect section. In more general terms, the instance section defines the logic, and the interconnect section defines routing information. For the Xilinx Virtex 5, the instance section comprises three types of instance names: IOBs, SLICEL/SLICEMs and XDL_DUMMY_IOI_*, where each instance configuration is identified with the key word “cfg”. Utilization of each instance is identified by the keyword “off”, which means this instance is not used, otherwise a value is associated with it. The description of configuration bits associated with each component within the SLICE, IOB and IOI instance is obtained using Xilinx’s FPGA editor and the Virtex 5 user guide [30]. Addition of configuration bits related to these instances leads to the overall estimate of configuration (care) bits in the logic.

The second section in the XDL file is related to interconnects, which is identified with the key word “pip”, which stands for Programmable Interconnect Point. Each pip keyword refers to a pass-transistor that is controlled by a configuration bit [30]. XDL file contains three different types of pip configuration, which are separated by keywords, CLBL, IOI and INT. It is found that the keywords CLBL, and IOI are related to connections involving CLBs and I/Os, respectively. Whereas INT represents connections involving switches only. To automate the decoding of the XDL file, we wrote a script in C to decode the number of configuration bits involved per XDL file of a design implemented in Xilinx Virtex 5, SRAM based FPGA.

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Thibeault, C., Hariri, Y., Hasan, S.R. et al. A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design. J Electron Test 29, 457–471 (2013). https://doi.org/10.1007/s10836-013-5393-9

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