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A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip

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Abstract

This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indicate how packets must detour thefaulty block. The most recent routing algorithm on this approach is Message-Route (Holsmark and Kumar J Inf Sci Eng 23:1649–1662, 2007) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. Moreover, an FPGA implementation of the proposed algorithm is also discussed.

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References

  1. Bertozzi D, Benini L (2004) Xpipes: a network-on-chip archi tecture for gigascale systems-on-chip. J IEEE Circuits Syst Mag 4(2):18–31

    Article  Google Scholar 

  2. Chen KH, Chiu G-M (1998) Fault-tolerant routing algorithm for meshes without using virtual channels. J Inf Sci Eng 14:765–783

    Google Scholar 

  3. Chiu G-M (2000) The odd-even turn model for adaptive routing. IEEE Trans Parallel Distrib Syst 11(7):729–738

    Article  Google Scholar 

  4. Duato J (1993) A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Trans Parallel Distrib Syst 4(12):1320–1331

    Article  Google Scholar 

  5. Glass CJ, Ni LM (1992) The turn model for adaptive routing. In: Proc. 19th Ann. Intl Symp. computer architecture, pp 278–287

  6. Glass CJ, Ni LM (1996) Fault-tolerant wormhole routing in meshes without virtual channels. IEEE Trans Parallel Distrib Syst 7(6):620–635

    Article  Google Scholar 

  7. Goossens K, Dielissen J, Rădulescu A (2005) Æ thereal network on chip: concepts, architectures, and implementations. J IEEE Des Test Comput 22(5):414–421

    Article  Google Scholar 

  8. Holsmark R, Kumar S (2007) Corrections to Chen and Chius fault tolerant routing algorithm for mesh networks. J Inf Sci Eng 23:1649–1662

    Google Scholar 

  9. Holsmark R, Palesi M, Kumar S (2008) Deadlock free rout ing algorithms for irregular mesh topology NoC systems with rectangular regions. J Syst Archit 54(3–4):427–440

    Article  Google Scholar 

  10. Kung S-Y, Jean S-N, Chang C-W (1989) Fault-tolerant array processors using single-track switches. IEEE Trans Comput 38(4):501–514

    Article  Google Scholar 

  11. Multicore processor based on iMesh architecture TILERA . http://www.tilera.com/products/processors

  12. Nurmi J, Tenhunen H, Isoaho J, Jantsch A (2004) Interconnect centric design for advanced SoC and NoC. Kluwer Academic Publishers, Norwell

    MATH  Google Scholar 

  13. Single Chip Cloud (SCC) project Intel . http://techresearch.intel.com/ProjectDetails.aspx?Id=1907

  14. Wu J (2003) A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model. IEEE Trans Comput 52(9):1154–1169

    Article  Google Scholar 

Download references

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Correspondence to Yusuke Fukushima.

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Responsible Editor: M. Violante

Appendix: Four Sub-Modules of Position-Route

Appendix: Four Sub-Modules of Position-Route

All four routing sub-modules of Position-Route is summarized in Fig. 26. Let C, D, and N be the current node, the destination node, and the direction of the output port, respectively. Notice that the underlined parts in the routing control can be pre-calculated. We use dot operator ’.’ to access members of RIUs, e.g. \(ne.tp\).

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Fukushima, Y., Fukushi, M. & Yairi, I.E. A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip. J Electron Test 29, 415–429 (2013). https://doi.org/10.1007/s10836-013-5377-9

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  • DOI: https://doi.org/10.1007/s10836-013-5377-9

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