Skip to main content
SpringerLink
Log in

Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

In this paper, we present a technique called Digital Captureless Delay Testing Sensors (DCDTS). This technique allows the detection of delay faults left uncovered by launch-on-capture transitions due to excessive resources (mainly test time or tester memory) requirements, with top-off random launch-on-shift patterns that do not require fast switching scan enable signals. The DCDTS random patterns are internally generated, requiring virtually no additional test application time or tester memory. As such, DCDTS can be seen as a new way to save both test time and tester memory. Results show that DCDTS can achieve pattern volume and test time reduction factors of up to 3. When used in complement to existing compression techniques, DCDTS has the potential to triple their pattern volume (test application time) compression (reduction) rate. Area/performance overhead and technical obstacles to automation are minimal. An automated sensor selection procedure is proposed, with reasonable CPU time.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5

Similar content being viewed by others

References

  1. Agarwal M, Paul BC, Zhang M, Mitra S (2007) “Circuit failure prediction and its application to transistor aging.” In Proc. of VTS, pp. 277–286

  2. Agarwal M, et al. (2007) “Circuit failure prediction and its application to transistor aging.” In Proc. VTS, pp. 277–284

  3. Ahmed N, Tehranipoor M (2006) Improving transition delay test using a hybrid method. IEEE Des Test 23(5):402–412

    Article  Google Scholar 

  4. Ahmed N, Tehranipoor M, Raviakumar CP (2005) “Enhanced launch-off-capture transition fault testing.” In Proc. IEEE ITC, pp. 246–255

  5. Chandra A, Yan H, Kapur R (2007) “Multimode Illinois scan architecture for test application time and test data volume reduction.” In Proc. VTS, pp. 84–92

  6. Cohen D, Banks C. “DATE: multi-clock design without risk.” In Electronics Weekly (electronicsweekly.com), 13 April 2009

  7. Devtaprasanna N, et al. (2005) “Improved delay fault coverage using subsets of flip-flops to launch transitions.” In Proc. ATS, pp. 202–207

  8. Devtaprasanna N, et al. (2005) “A novel method of improving transition delay fault coverage using multiple scan enable signals.” In Proc. International Conference on Computer Design, pp. 471–474

  9. Geuzebroek MJ, Linden JTV, van de Goor AJ (2002) “Test point insertion that facilitates ATPG in reducing test time and data volume.” In Proc. Int. Test Conf, pp. 138–147

  10. Ghosh S, Bhunia S, Raychowdhury A, Roy K (2006) A novel delay fault testing methodology using low-overhead built-in delay sensor. IEEE Trans Comput Aided Des Integrated Circ Syst 25(12):2934–2943

    Article  Google Scholar 

  11. Gupta P, et al. (2003) “Layout-aware scan chain synthesis for improved path delay fault coverage.” In Proc. ICCAD, pp. 754–759

  12. Hetherington G, et al. (1999) “Logic BIST for large industrial designs: real issues and case studies.” In Proc. ITC, pp. 358–367

  13. Iyengar V, et al. (2006) “At-speed structural test for high-performance ASICs.” In Proc. ITC, pp. 1–10

  14. Jain V, Waicukauski J (2002) “Scan test data volume reduction in multi-clocked designs with safe capture technique.” In Proc. ITC, pp. 148–153

  15. Kapur R, Mitra S, Williams TW (2008) Historical perspective on scan compression. IEEE Des Test Comput 25(2):114–120

    Article  Google Scholar 

  16. Kim KS et al (2003) Delay defect characteristics and testing strategies. IEEE Des Test 20(5):8–16

    Article  Google Scholar 

  17. Kusko MP, et al. (2001) “99% AC test coverage using BIST only on the 1 GHz IBM S/390 zSeries 900 microprocessor.” In Proc. ITC, pp. 586–592

  18. Lin X et al (2003) High-frequency, at-speed scan testing. IEEE Des Test 20(5):17–25

    Article  Google Scholar 

  19. Madge R, et al. (2004) “In search for the optimum test set–adaptive test methods for maximum defect coverage and lowest test cost.” In Proc. ITC, pp. 203–212

  20. Mak TM et al (2004) New challenges in delay testing of nanometer, multigigahertz designs. IEEE Des Test 21(3):241–247

    Article  Google Scholar 

  21. Mehta VJ, Marek-Sadowska M, Tsai K-H, Rajski J (2008) Improving the resolution of single-delay-fault diagnosis. IEEE Trans Comput Aided Des Integrated Circ Syst 27(5):932–945

    Article  Google Scholar 

  22. Nakao M, Kobayashi S, Hatayama K, Iijima K, Terada S (1999) “Low overhead test point insertion for scan-based BIST.” In Proc. ITC, pp. 348

  23. Pan M, Chu C. “FastRoute 2.0: a high-quality and efficient global router.” Proc. of Asia and South Pacific Design Automation Conf., Jan 2007, pp. 250–255

  24. Pateras S (2003) Achieving at-speed structural test. IEEE Des Test 20(5):26–33

    Article  Google Scholar 

  25. Pomeranz I, Reddy S (1998) Design for testability or path delay faults in large combinational circuits using test points. IEEE Trans Comput Aided Des Integrated Circ Syst 17(4):333–343

    Article  Google Scholar 

  26. Saxena J, et al. (2002) “Scan-based transition fault testing–implementation and low cost challenges.” In Proc. ITC, pp. 1120–1129

  27. Thibeault C (2008) “On a dynamic monitoring approach for power noise.” Proc. D3T

  28. Thibeault C. “Improving digital IC testing with analog circuits.” IEEE NEWCAS Conf., June 2006, pp. 285–288

  29. Thibeault C, Hariri Y, Hobeika C (2009) “On captureless delay test points.” In Proc. of NEWCAS-TAISA ’09, pp. 1–4

  30. Touba NA (2006) Survey of test vector compression techniques. IEEE Des Test Comput 23(4):294–303

    Article  Google Scholar 

  31. Tragoudas S, Denny N (1999) “Testing for path delay faults using test points.” In Proc. Int. Symp. Defect and Fault Tolerance in VLSI Systems, pp. 79–85

  32. Tsai HC, Cheng KT, Agrawal VD (2000) “A testability metric for path delay faults and its application.” In Proc. Asia South Pacific Des. Autom. Conf., pp. 593–598

  33. Vranken H, Sapei FS, Wunderlich H-J (2004) “Impact of test point insertion on silicon area and timing during layout.” In Proc. DATE in Europe

  34. Wang S, Liu X, Chakradhar ST (2004) “Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets.” In Proc. DATE in Europe, pp. 1296–1301

  35. Xu G, Singh AD (2007) “Delay test scan flip-flop: DFT for high coverage delay testing.” In Proc. VLSI Design Conf, pp. 763–768

  36. Yan G, Han Y, Li X. “A unified online fault detection scheme via checking of stability violation.” DATE, April 2009, pp. 496–501

  37. Yan G, Han Y, Liu H, Liang X, Li X (2009) “MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency.” In Proc. of ISLPED ’09, pp. 395–400

  38. Yan G, et al. (2009) “A unified online fault detection scheme via checking of stability violation.” In Proc. DATE, pp. 395–400

  39. Yang F, et al. (2008) “On the detectability of scan chain interval faults.” In Proc. VTS, pp. 79–85

Download references

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, École de Technologie Supérieure, Montreal, QC, Canada

    C. Thibeault, Y. Hariri & C. Hobeika

Authors
  1. C. Thibeault
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Y. Hariri
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. C. Hobeika
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to C. Thibeault.

Additional information

Responsible Editor: M. Tehranipoor

Appendices

Appendix A

As mentioned in section 3, the sensors (S) detect “illegal” transitions. The circuit-level implementation of the sensor is shown in Fig. 6.

Fig. 6
figure 6

Sensor implementation

Full size image

While the clk signal is high, the sensor is in its memorizing/precharging phase: the pass transistor is on, forcing na = nb and nz (and n1) to precharge at 1 if out = 0. Note that if out = 1, it means that nz = 1 and does not need to be precharged. When the clk signal is low, the sensor is in its evaluation phase: the pass transistor is off and the nz signal remains at 1 unless the NMOS evaluation network pulls it down toward 0. This will happen if an illegal transition is detected on the in signal. In that case, the out signal will go down, and this pulse will be propagated through the daisy chain until it reaches the chain output (out_ds, see Fig. 1). This propagation is made possible by the ny signal connected to the output of the previous sensor in the chain. Note that the feedback loop created by the out signal is there to ensure that a large enough negative pulse (to 0) is sent to the next sensor, in case an illegal transition is detected close to the clock rising edge.

Appendix B

Here we present results validating the assumption according to which (LOS) random patterns provide similar coverage as the DCDTS (random) ones. For that we created actual DCDTS test patterns from the shifting LOC patterns. We targeted the B14 circuit, as it is the one with the smallest number of LOC (and DCDTS) patterns and that differences between two sets of random patterns are more likely to occur with a limited number of patterns. The results appear in Fig. 7. These results clearly show that, at the end, the difference between the two sets of patterns is very small, corresponding to a coverage error estimation of only 0.11%. We expected this difference to be as low or even lower with longer random pattern sequences.

Fig. 7
figure 7

Additional number of covered faults as a function of the number of test patterns: (LOS) random vs. DCDTS patterns

Full size image

Rights and permissions

Reprints and permissions

About this article

Cite this article

Thibeault, C., Hariri, Y. & Hobeika, C. Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors. J Electron Test 28, 229–242 (2012). https://doi.org/10.1007/s10836-011-5271-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-011-5271-2

Keywords

Search

Navigation