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Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding

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Abstract

Network on Chip (NoC) is an enabling methodology of integrating a very high number of intellectual property (IP) blocks in a single System on Chip (SoC). A major challenge that NoC design is expected to face is the intrinsic unreliability of the interconnect infrastructure under technology limitations. Research must address the combination of new device-level defects or error-prone technologies within systems that must deliver high levels of reliability and dependability while satisfying other hard constraints such as low energy consumption. By incorporating novel error correcting codes it is possible to protect the NoC communication fabric against transient errors and at the same time lower the energy dissipation. We propose a novel, simple coding scheme called Crosstalk Avoiding Double Error Correction Code (CADEC). Detailed analysis followed by simulations with three commonly used NoC architectures show that CADEC provides significant energy savings compared to previously proposed crosstalk avoiding single error correcting codes and error-detection/retransmission schemes.

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Authors and Affiliations

  1. School of Electrical Engineering & Computer Science, Washington State University, PO BOX 642752, Pullman, WA, USA

    Amlan Ganguly, Partha Pratim Pande & Benjamin Belzer

  2. SoC Research Lab, University of British Columbia, 2332 Main Mall, Vancouver, BC, V6T 1Z4, Canada

    Cristian Grecu

Authors
  1. Amlan Ganguly
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  2. Partha Pratim Pande
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  3. Benjamin Belzer
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  4. Cristian Grecu
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Correspondence to Amlan Ganguly.

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Responsible Editor: N. A. Touba

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Ganguly, A., Pande, P.P., Belzer, B. et al. Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding. J Electron Test 24, 67–81 (2008). https://doi.org/10.1007/s10836-007-5035-1

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  • DOI: https://doi.org/10.1007/s10836-007-5035-1

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