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Automatic Test Pattern Generation for Resistive Bridging Faults

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Abstract

An ATPG for resistive bridging faults in combinational or full-scan circuits is proposed. It combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle static effects of arbitrary non-feedback bridges between two nodes, including ones detectable at higher bridge resistance and undetectable at lower resistance, and faults requiring more than one vector for detection. The developed tool is applied to ISCAS circuits, and a higher efficiency compared with other resistive bridging fault as well as stuck-at ATPG is reported. Information required for accurate resistive bridging fault simulation is obtained as a by-product.

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Authors and Affiliations

  1. Institute of Computer Science, Albert-Ludwigs-University, Georges-Köhler-Allee 51, 79110, Freiburg im Breisgau, Germany

    Piet Engelke, Ilia Polian & Bernd Becker

  2. LIRMM – UMII, 161 Rue Ada, 34392, Montpellier, France

    Michel Renovell

Authors
  1. Piet Engelke
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  2. Ilia Polian
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  3. Michel Renovell
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  4. Bernd Becker
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Correspondence to Piet Engelke.

Additional information

Editor: C. Landrault

Piet Engelke received his diploma in computer science from the University of Freiburg in 2002. He stayed with the same university, to continue his research on resistive bridging faults and is currently working towards his Ph.D. In 2004 and 2005 he was part of the Design For Test group of Mentor Graphics Corp., Wilsonville, OR. His research interests include defect based testing and fault simulation.

Ilia Polian received his Ph.D. degree in Computer Science (with distinction) from the Albert-Ludwigs-University of Freiburg, Germany, in 2003 and diploma (master’s) degree in 1999 from the same University. Currently he is a senior member of scientific staff at the Chair of Computer Architecture at the Albert-Ludwigs-University. His previous affiliations were Micronas in Freiburg, IBM Germany R&D in Böblingen and NAIST in Nara, Japan. He was European Champion and Vice World Champion at the 1999 ACM International Collegiate Programming Contest, VDE award laureate 1999 and Wolfgang-Gentner award laureate 2005. His research interests include defect modeling, design for testability and formal verification of hybrid and real-time systems.

Michel Renovell received his PhD degree in 1986 in Electronics Engineering. He is now researcher with the CNRS (French National Council for Scientific Research). He is a member of the editorial board of JETTA and the editorial board of IEEE Design & Test. He has been Vice-Chair of the IEEE TTTC (Test Technology Technical Council). Michel has been General Chair of several conferences: International Mixed Signal Testing Workshop IMSTW2000, Field Programmable Logic Conference FPL2002, IEEE European Test Symposium ETS2004. His research interests include: Defect modeling, Analog testing and FPGA testing.

Bernd Becker studied Mathematics and Computer Science at the University of Saarland, Germany, from 1973 to 1982. Between 1979 and 1988, he was with the Sonderforschungsbereich “Electronic Speech Recognition” (79–81), “Institute for Computer Science and Applied Mathematics” (81–83) and the Sonderforschungsbereich “VLSI Design Methods and Parallelism” (84–88), all at the University of Saarland. From 1989 to 1995, he was an Associate Professor for “Complexity Theory and Efficient Algorithms” at the J.W. Goethe-University Frankfurt. In 1995, he joined the Faculty of Applied Sciences at the Albert-Ludwigs-University Freiburg as a Full Professor (Chair of Computer Architecture). His research interests include data structures and efficient algorithms (for circuit design), design, test and verification of circuits and systems, multimedia in research and teaching.

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Engelke, P., Polian, I., Renovell, M. et al. Automatic Test Pattern Generation for Resistive Bridging Faults. J Electron Test 22, 61–69 (2006). https://doi.org/10.1007/s10836-006-6392-x

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  • DOI: https://doi.org/10.1007/s10836-006-6392-x

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