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Parallel Programming of Multi-processor SoC: A HW–SW Interface Perspective

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For the design of classic computers the parallel programming concept is used to abstract HW/SW interfaces during high level specification of application software. The software is then adapted to existing multiprocessor platforms using a low level software layer that implements the programming model. Unlike classic computers, the design of heterogeneous MPSoC includes also building the processors and other kind of hardware components required to execute the software. In this case, the programming model hides both hardware and software refinements. This paper deals with parallel programming models to abstract both hardware and software interfaces in the case of heterogeneous MPSoC design. Different abstraction levels will be needed. For the long term, the use of higher level programming models will open new vistas for optimization and architecture exploration like CPU/RTOS tradeoffs.

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Authors and Affiliations

  1. SLS Group, TIMA Laboratory, 46 Avenue Félix Viallet, 38031, Grenoble, France

    Lobna Kriaa, Aimen Bouchhima, Marius Gligor, Fréderic Pétrot & Ahmed-Amine Jerraya

  2. THALES, Land & Joint Systems EDS/DHD 146, Boulevard de Valmy, 92704, Colombes cedex, France

    Anne-Marie Fouillart

Authors
  1. Lobna Kriaa
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  2. Aimen Bouchhima
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  3. Marius Gligor
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  4. Anne-Marie Fouillart
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  5. Fréderic Pétrot
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  6. Ahmed-Amine Jerraya
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Correspondence to Lobna Kriaa.

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Kriaa, L., Bouchhima, A., Gligor, M. et al. Parallel Programming of Multi-processor SoC: A HW–SW Interface Perspective. Int J Parallel Prog 36, 68–92 (2008). https://doi.org/10.1007/s10766-007-0042-5

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  • DOI: https://doi.org/10.1007/s10766-007-0042-5

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