Skip to main content
SpringerLink
Log in

Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper presents a detailed scaling analysis of the power supply distribution network voltage drop in DSM technologies. The effects of chip temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the voltage drop effect in the power/ground (P/G) distribution network increases rapidly with technology scaling, and that using well-known countermeasures such as wire-sizing and/or decoupling capacitor insertion which are typically used in the present design methodologies may be insufficient to limit the voltage fluctuations over the power grid for future technologies. It is also shown that such voltage drops on power supply lines of switching devices in a clock distribution network can introduce significant amount of skew which in turn degrades the signal integrity.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. R. Saleh, S.Z. Hussain, S. Rochel, and D. Overhauser, “Clock skew verification in the presence of IR-Drop in the power distribution network.” IEEE Trans. on Computer-Aided Design, vol. 19, no. 6, pp. 635–644, 2000.

    Google Scholar 

  2. A. Chandrakasan, W.J. Bowhill F. Fox, Design of High-Performance Microprocessor Circuits. IEEE Press, 2001.

  3. A. Dharchoudhury, R. Panda, D. Blaauw, R. Vaidyanathan, “Design and analysis of power distribution network on PowerPC microprocessor.” in Proc. of Design Automation Conference, 1998, pp. 738–743.

  4. M. Iwabuchi, N.Sakamoto, Y.Sekine, T.Omachi, “A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design.” in Proc. of Int’l Symposium on Physical Design, 1999, pp. 9–15.

  5. A. Dalal, L. Lev, S. Mitra, “Design of an efficient power distribution network for the UltraSPARC-I™ microprocessor.” in Proc. Int’l. Conf. on Computer Design: VLSI in Computers and Processors, 1995, pp. 118–123.

  6. X. Tan, C.J.R. Shi, D. Lungeanu, J. Lee, and L. Yuan, “Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programming.” in Proc. of Design Automation Conference, 1999, pp. 78–83.

  7. T. Mitsuhashi and E.S. Kuh, “Power and ground network topology optimization for cell-based VLSI.” in Proc. of Design Automation Conference, 1992, pp. 524–529.

  8. H.H. Chen and J.S. Neely, “Interconnect and circuit modeling techniques for full-chip power supply noise analysis.” IEEE Trans. on Components, Packaging, and Manufacturing, vol. 21, no. 3, pp. 209–215, 1998.

    Google Scholar 

  9. S.R. Nassif and J.N. Kozhaya, “Fast power grid simulation,” in Proc. of Design Automation Conference, 2000, pp. 156-161.

  10. R. Chaudhry, D. Blaauw, R. Panda, and T. Edwards “Current signature compression for IR-drop analysis,” in Proc. of Design Automation Conference, 2000, pp. 162–167.

  11. M.D. Pant, P. Pant, and D.S. Wills, “On-chip decoupling capacitor optimization using architectural level current signature prediction,” in Proc. Int’l. ASIC/SOC Conference, 2000, pp 288–292.

  12. H.H. Chen and D.D. Ling, “Power supply noise analysis methodology for deep-submicron VLSI chip design,” in Proc. Design Automation Conference, 1997, pp. 638–643.

  13. S. Im and K. Banerjee, “Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs,” Technical Digest Int’l Electron Device Meetring, pp. 727–730, 2000.

  14. D. Luenberger, Linear and Nonlinear Programming, 2nd edition, Addison-Wesley Pub. Company, 1984.

  15. P. Chahal, R.R. Tummala, M.G. Allen, and M. Swaminathan, “A Novel integrated decoupling capacitor for MCM-L technology.” IEEE Trans. on Components, Packaging, and Manufacturing, vol. 21, no. 2, pp. 184–193, 1998.

    Google Scholar 

  16. C.S. Chang, A. Oscilowski, and R.C. Bracken, “Future challenges in electronics packaging.” IEEE Trans. on Circuits and Devices, vol. 14, no. 2, pp. 45–54, 1998.

    Google Scholar 

  17. Applications of Metal-Insulator-Metal (MIM) Capacitors, International SEMATECH, Technology transfer 00083985AENG.

  18. J.R. Black, “Electromigration—A brief survey and some recent results.” IEEE Trans. on Electron Devices, vol. ED-16, pp. 338–347, 1969.

    Google Scholar 

  19. K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu, “On thermal effects in deep sub-micron VLSI interconnects,” in Proc. Design Automation Conference, 1999, pp. 885–891.

  20. S. Rzepka, K. Banerjee, E. Meusel, and C. Hu, “Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation.” IEEE Trans. on Components, Packaging and Manufacturing Technology-A, vol. 21, no. 3, pp. 406–411, 1998.

    Google Scholar 

  21. International Technology Roadmap for Semiconductors. ITRS, 2001.

  22. J.C. Anderson, The Use of Thin Films in Physical Investigation. Academic Press, 1966.

  23. K. Banerjee, S.J. Souri, P. Kapur, and K.C. Saraswat, “3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration.” in Proc. of the IEEE, Special Issue, Interconnections—Addressing The Next Challenge of IC Technology, vol. 89, no. 5, pp. 602–633, 2001.

    Google Scholar 

  24. C.H. Tsai and S.M. Kang, “Cell-level placement for improving substrate thermal distribution.” IEEE Trans. on Computer Aided Design, vol 19, no. 2, pp 253–265, 2000.

    Google Scholar 

  25. A.H. Ajami, K. Banerjee, M. Pedram, and L.P.P.P. van Ginneken, “Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs.” in Proc. Design Automation Conference, 2001, pp. 567–572.

  26. K. Toh, P. Ko, and R. Meyer, “An empirical model for short-channel MOS devices.” IEEE Journal of Solid-States Circuits, vol. 23, pp. 2950–2957, 1988.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Magma Design Automation, 5460 Bay Front Plaza, Santa Clara, CA, 95054

    Amir H. Ajami

  2. ECE Dept., 4151 Eng I, Univ. of California at Santa Barbara, Santa Barbara, CA, 93106

    Kaustav Banerjee

  3. EE-Systems Dept., 3740 McClintock Ave, Univ. of Southern California, Los Angeles, CA, 90089

    Massoud Pedram

Authors
  1. Amir H. Ajami
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Kaustav Banerjee
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Massoud Pedram
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Amir H. Ajami.

Additional information

This work was done when the author was with the Dept. of EESystems, University of Southern California.

Amir H. Ajami received his B.S. degree in electrical engineering from the University of Tehran, Tehran, Iran in 1993. He received his M.S. and Ph.D. degrees in electrical engineering from the University of Southern California, Los Angeles, CA, in 1999 and 2002, respectively.

He is currently a member of consulting staff in research and development division at MagmaDesign Automation, Inc., Santa Clara, CA. He has previously held positions at Cadence Design Systems, Inc., andMagma Design Automations, Inc., in 1999 and 2000, respectively. His research interests are in the area of technology scaling issues in high-performance VLSI designs with emphasis on full-chip thermal analysis, thermalaware timing and power optimization methodologies, and signal integrity. He has coauthored several papers on the modeling and analysis of the effects of substrate thermal gradients on performance degradation and development of thermal-aware physical-synthesis optimization algorithms.

Dr. Ajami is a member of Association of Computing Machinery (ACM) and IEEE. HE serves on the technical program committee of the 2005 IEEE International Symposium on Quality Electronics Design.

Kaustav Banerjee received the Ph.D. degree in electrical engineering and computer sciences from the University of California at Berkeley in 1999. He was with Stanford University, Stanford, CA, from 1999 to 2002 as a Research Associate at the Center for Integrated Systems. In July 2002, he joined the faculty of the Electrical and Computer Engineering Department at the University of California, Santa Barbara, as an Assistant Professor. From February 2002 to August 2002 he was a Visiting Professor at the Circuit Research Labs of Intel in Hillsboro, Oregon. In the past, he has also held summer/visiting positions at Texas Instruments Inc., Dallas, Texas, Fujitsu Labs and the Swiss Federal Institute of Technology (EPFL). His present research interests focus on a wide variety of nanometer scale issues in high-performance VLSI and mixed-signal designs, as well as on circuits and systems issues in emerging nanoelectronics. He is also interested in some exploratory interconnect and circuit architectures including 3-D ICs. At UCSB, Dr. Banerjee mentors several doctoral and masters students. He also co-advises graduate students at Stanford University, University of Illinois at Urbana-Champaign and EPFL-Switzerland. He has co-directed two doctoral dissertations at Stanford University and the University of Southern California. Dr. Banerjee served as Technical Program Chair of the 2002 IEEE International Symposium on Quality Electronic Design (ISQED ‘02), and is the General Chair of ISQED ‘05. He also serves or has served on the technical program committees of the IEEE International Electron Devices Meeting, the IEEE International Reliability Physics Symposium, the EOS/ESD Symposium and the ACM International Symposium on Physical Design. His research has been chronicled in over 100 journals and refereed international conference papers and a book chapter. He has also co-edited a book titled “ Emerging Nanoelectronics: Life with and after CMOS” by Kluwer in 2004. Dr. Banerjee has been recognized through the ACM SIGDA Outstanding New Faculty Award (2004) as well as a Best Paper Award at the Design Automation Conference (2001). He is listed in Who’s Who in America and Who’s Who in Science and Engineering.

Massoud Pedram received a B.S. degree in Electrical Engineering from the California Institute of Technology in 1986 and M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley in 1989 and 1991, respectively. He then joined the department of Electrical Engineering, Systems at the University of Southern California where he is currently a professor. Dr. Pedram has served on the technical program committee of a number of conferences, including the Design automation Conference (DAC), Design and Test in Europe Conference (DATE), Asia-Pacific Design automation Conference (ASP-DAC), and International Conference on Computer Aided Design (ICCAD). He served as the Technical Co-chair and General Co-chair of the International Symposium on Low Power Electronics and Design (SLPED) in 1996 and 1997, respectively. He was the Technical Program Chair and the General Chair of the 2002 and 2003 International Symposium on Physical Design. Dr. Pedram has published four books, 60 journal papers, and more than 150 conference papers. His research has received a number of awards including two ICCD Best Paper Awards, a Distinguished Citation from ICCAD, a DAC Best Paper Award, and an IEEE Transactions on VLSI Systems Best Paper Award. He is a recipient of the NSF’s Young Investigator Award (1994) and the Presidential Faculty Fellows Award (a.k.a. PECASE Award) (1996).

Dr. Pedram is a Fellow of the IEEE, a member of the Board of Governors for the IEEE Circuits and systems Society, an associate editor of the IEEE Transactions on Computer Aided Design, the IEEE Transactions on Circuits and Systems, and the IEEE Circuits and Systems Society Distinguished Lecturer Program Chair. He is also an Advisory Board Member of the ACM Interest Group on Design Automation, and an associate editor of the ACM Transactions on Design Automation of Electronic Systems. His current work focuses on developing computer aided design methodologies and techniques for low power design, synthesis, and physical design. For more information, please go to URL address: http://atrak.usc.edu/~massoud/.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Ajami, A.H., Banerjee, K. & Pedram, M. Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI. Analog Integr Circ Sig Process 42, 277–290 (2005). https://doi.org/10.1007/s10470-005-6761-x

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-005-6761-x

Keywords

Search

Navigation