Benchmarking for power consumption monitoring

Abstract

This paper presents a set of benchmarks that are designed to measure power consumption in parallel systems. The benchmarks range from low-level, single instructions or operations, to small kernels. In addition to describing the motivation behind developing the benchmarks and the design principles that were followed, the paper also introduces a metric to quantify the power-performance of a parallel system. Initial results are presented and help to illustrate the contribution of the paper.

Appendix: ODROID specifications

The board used in the evaluation section of this paper is an ODROID XU+E. This is a complete System-on-Chip based on the Samsung Exynos 5410 Octa processor with two quad-core ARM CPUs [8]: the performance CPU, a complex out-of-order ARM A15 running at 1.6 GHz, and the powersaving CPU, a simple in-order ARM A7, with a clock speed of 200 MHz. Both CPUs have 32 KB L1 instruction and data caches per compute core. However the L2 cache (which is shared between all core of the CPU) for the A15 is 2 MB, as opposed to only 512 KB for the A7. The ODROID has 2 GB of LPDDR3 DRAM, which runs at 800 MHz and has a maximum bandwidth of 12.8 GB/s. Ordinarily, the system is free to migrate loads between processors, however, for all results in this paper the load (the benchmark) was fixed to one CPU.

The ODROID has built-in power measurement sensors for both the SoC and board, allowing easy access to power usage data without external instrumentation. These sensors can measure the voltage, current and power consumption of each the CPUs, as well as the memory and the on-board GPU. The sensor readings are reported via the Linux filesystem. The update period for the sensors is set to the default of 262 ms although it can be lowered to measure shorter loads at a cost of an increased overhead in sampling, as for any in-band measurement system. The measurements themselves are taken by INA231 sensor modules from TI which use 16 bit ADCs with an accuracy of $2.5~\upmu \hbox {V}$.

A block diagram for the ODROID is shown in Fig. 8.

Fig. 8

ODROID block diagram, courtesy of HardKernel