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Evaluation of CPU frequency transition latency

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Computer Science - Research and Development

Abstract

Dynamic Voltage and Frequency Scaling (DVFS) has appeared as one of the most important techniques to reduce energy consumption in computing systems. The main idea exploited by DVFS controllers is to reduce the CPU frequency in memory-bound phases, usually significantly reducing the energy consumption. However, depending on the CPU model, transitions between CPU frequencies may imply varying delays. Such delays are often optimistically ignored in DVFS controllers, whereas their knowledge could enhance the quality of frequency setting decisions.

The current article presents an experimental study on the measurement of frequency transition latencies. The measurement methodology is presented accompanied with evaluations on three Intel machines, reflecting three distinct micro-architectures. In overall, we show for our experimental setup that, while changing CPU frequency upward leads to higher transition delays, changing it downward leads to smaller or similar transition delays across the set of available frequencies.

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Notes

  1. Experimental setup in Sect. 4.

  2. 2.776 is the t distribution value for a 95 % confidence level.

  3. Confidence intervals overlap but the mean of either is outside the confidence interval of the other.

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Acknowledgements

We would like to thank Jamel Tayeb from Intel Portland for its kind help in the design of processor energy measurement probes.

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Authors and Affiliations

  1. Univ. Versailles St-Quentin en Yvelines, Versailles cedex, France

    Abdelhafid Mazouz, Alexandre Laurent, Benoît Pradelle & William Jalby

Authors
  1. Abdelhafid Mazouz
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  2. Alexandre Laurent
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  3. Benoît Pradelle
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  4. William Jalby
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Correspondence to Abdelhafid Mazouz.

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Mazouz, A., Laurent, A., Pradelle, B. et al. Evaluation of CPU frequency transition latency. Comput Sci Res Dev 29, 187–195 (2014). https://doi.org/10.1007/s00450-013-0240-x

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