Multilayer ion trap with three-dimensional microwave circuitry for scalable quantum logic applications

Abstract

We present a multilayer surface-electrode ion trap with embedded 3D microwave circuitry for implementing entangling quantum logic gates. We discuss the electromagnetic full-wave simulation procedure that has led to the trap design and the characterization of the resulting microwave field pattern using a single ion as a local field probe. The results agree with simulations within the uncertainty; compared to previous traps, this design reduces detrimental AC Zeeman shifts by three orders of magnitude. The design presented here can be viewed as an entangling gate component in a library for surface-electrode ion traps intended for quantum logic operations.

Appendix: Joule heating

When microwave currents are applied to the trap through a conductor with finite conductivity, electric energy is converted into heat through resistive losses. Excessive resistive heating in the trap might lead to a degeneration of its performance or, in extreme cases, to an irreversible damage of the conductor. This is especially critical for an ion trap with multiple layers as discussed here, since current-carrying conductors defined around the geometric trap center have relatively narrow lateral dimensions, i.e., poor thermal contact to the substrate.

To include thermal effects caused by applying short microwave pulses with high power to the MWM conductor imitating real experimental conditions, one would need to numerically solve a complex system, including the whole chip geometry and inductive heating caused on neighbouring electrodes. However, it is also possible to gain insight into thermal effects in the trap design using a simplified model in which a constant DC current is applied to MWM. As already introduced in Sect. 3.1, we make use of a pocket in the three segments of MWM with length $l_{\text {m}}$ to further decrease the residual magnetic field B at the ion’s position. Since we are interested in a compromise between a sufficiently low heat load and low B, the simplified DC power model still reveals the qualitative behaviour of the system.

In the experiment we apply $1.9\,$W to the MWM structure corresponding to c.a. $160\,$mW of power not reflected by the trap given the measured S-parameter, see caption of Fig. 6. To better understand the limits of thermal dissipation we perform simulations on a DC current in a similar structure. We use a current of $1\,$A which corresponds to a dissipated power of $200\,{\text {mW}}$ since the nominal geometry considered in the model, $l_{\text {th}}={200}\,\upmu {\text {m}}$, has a resistance of $0.2\, \Omega$.

Fig. 7

Results of the simplified finite-element model in which a constant current of $1\,$A is applied to MWM. The plots show the temperature increase in the center of MWM as a function of excitation time. Different colors indicate a different pocket length $l_{\text {th}}$

The numerical simulations are performed using the AC/DC and heat transfer modules of COMSOL 4.3, assuming a DC current of 1 A applied to MWM, supported on an ${\text {Si}}_3{\text {N}}_4$/Si substrate of $1.5\,{\text {mm}}\times 1.5\,{\text {mm}}$. We perform a parametric sweep of $l_{\text {th}}$ along the y-axis. As a result of the fabrication process, the pockets are filled with a dielectric material, which we included in the model assuming a thermal conductivity of $0.15\,{\text {W}}\,{\text {m}}^{-1} \, {\text {K}}$. The electrical and thermal properties of Au (conductor material) and ${\text {Si}}_3{\text {N}}_4$ (wafer material) are taken from the built-in materials data library. While the room temperature ($T_0 = 293.15\, {\text {K}}$) reference is defined to be at the backside of the chip trap, the temperature of MWM is monitored on the surface of ${L}_2$ at the geometric trap center marked as ‘X’ in Fig. 1c. At this position the heat load is maximal because each segment of MWM vertically splits into two parts of thickness $h_1$ and $h_3$, respectively, separated by the pocket of thickness $h_2$ in the interconnect layer ${V}_1$ filled with the dielectric material (see inset Fig. 1c). Naturally, at this point the heat will be poorly transported along the x-axis perpendicular to the trap.

Fig. 8

Residual magnetic field B for different pocket lengths $l_{\text {th}}$ in the segments of the MWM conductor. At about $l_{\text {th}}=200\,\upmu {\text {m}}$ there is no further decrease in the residual field. The values were obtained by performing FEM simulations using our simulation model discussed in Sect. 3.2

Figure 7 shows the resulting temperature change with respect to room temperature for different values of $l_{\text {th}}$ as a function of time. For $l_{\text {th}}=200\,{\upmu {\text {m}}}$, the system reaches a steady state after $0.6\,{\text {ms}}$, increasing its temperature by $17\,{\text {K}}$. As shorter values for $l_{\text {th}}$ decrease the temperature change, but increase B at the ion position (see Sect. 3.1), we found $l_{\text {th}}=200\,\upmu {\text {m}}$ to be the best compromise as illustrated in Fig. 8.