Abstract
The Full Adder is one of the most important and basic units of mathematic circuits that is the basic structure of many complex systems. Moreover, serial and serial-parallel mathematic processes can be carried out faster and more operative error-detection and error-correction codes can be employed in ternary logic implementations. In this work, we presented a new high-performance Ternary Full Adder (TFA) based on Carbon Nanotube Field-Effect Transistor (CNTFET) technology. The proposed design is well-matched with the Carbon Nanotube Field-effect Transistor knowledge and ternary logic value. The presented structure reduces the delay of the Ternary Full Adder and has high driving capability. The proposed Ternary Full Adder is simulated at varying supply voltages and temperatures using different frequencies by the Synopsys HSPICE circuit simulator. Simulation results determine improvement in terms of delay and Power-Delay Product (PDP) in comparison with the state-of-the-art designs. Simulations show that the proposed Ternary Full Adder cell shows approximately more than 53 % improvement in PDP compared to its counterparts.
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Keshavarzian, P., Sarikhani, R. A Novel CNTFET-based Ternary Full Adder. Circuits Syst Signal Process 33, 665–679 (2014). https://doi.org/10.1007/s00034-013-9672-6
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DOI: https://doi.org/10.1007/s00034-013-9672-6