Minimization of Via-Induced Signal Reflection in On-Chip High Speed Interconnect Lines

Abstract

Vias are extensively used to connect different metal levels in a multilayered Integrated Circuits (IC). The impedance discontinuities at the junction of the interconnect and via results in signal reflections and create signal integrity problems. This is one of the important design issues in ICs operating at gigahertz (GHz) frequencies. In this paper, a method for the reduction of via-induced signal reflection in high-speed on-chip intermediate/global interconnect structures is proposed. Signal reflection minimization is achieved through impedance matching by the inclusion of an appropriate capacitive load at the interconnect–via junction. This method is demonstrated for a two-layer interconnect structure connected through a via. The proposed solution reduces the signal reflection to as low as −35 dB at the tuned frequency of 5 GHz and less than −10 dB in its vicinity (1 to 10 GHz). The operating frequency can be changed by tuning the matching capacitive load and hence this method can be extended to any high frequency operation by digitally tuning a bank of on-chip capacitors (without going through a new fabrication run). Further it is shown that the signal reflections are reduced considerably in a six-layer structure and hence this method can be extended to any multi-level interconnect structure.