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About this book
Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability.
The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.
Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.
Authors and Affiliations
Bibliographic Information
Book Title: Direct Transistor-Level Layout for Digital Blocks
Authors: Prakash Gopalakrishnan, Rob A. Rutenbar
DOI: https://doi.org/10.1007/b117054
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Springer Science+Business Media New York 2004
Hardcover ISBN: 978-1-4020-7665-7Published: 17 June 2004
Softcover ISBN: 978-1-4757-7951-6Published: 23 March 2013
eBook ISBN: 978-1-4020-8063-0Published: 16 January 2006
Edition Number: 1
Number of Pages: IX, 125
Topics: Circuits and Systems, Electrical Engineering, Computer-Aided Engineering (CAD, CAE) and Design