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Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

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Abstract

Two-dimensional (2D) analytical models for the subthreshold current and␣subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable␣boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.

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Acknowledgements

The authors thank the Science and Engineering Research Board (SERB), Department of Science and Technology (DST), Govt. of India, for their financial support to do this work (Project No. SERB/ET-0415/2012). The simulation results were carried out at Device Simulation Laboratory, National Institute of Technology, Rourkela.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, St. Martin’s Engineering College, Secunderabad, Telangana, 500014, India

    Gopi Krishna Saramekala

  2. Department of Electrical Engineering, Indian Institute of Technology Patna, Bihta, Patna, Bihar, 801103, India

    Pramod Kumar Tiwari

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  1. Gopi Krishna Saramekala
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  2. Pramod Kumar Tiwari
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Correspondence to Pramod Kumar Tiwari.

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Saramekala, G.K., Tiwari, P.K. Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control. J. Electron. Mater. 46, 5046–5056 (2017). https://doi.org/10.1007/s11664-017-5508-7

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  • DOI: https://doi.org/10.1007/s11664-017-5508-7

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