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Resilient design of current steering DACs using a transistor level approach

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Abstract

The integrated circuit industry not only demands finding optimal design solutions over an efficient process, but also requires the address of increased reliability challenges, caused by strong electric fields, to elevate the overall system robustness. This work reconciles such an inconsistency by proposing a transistor-level methodology for current steering DACs to map their specs onto transistor sizes and improve their performance, parametric yield as well as lifetime reliability through the state of the art evolutionary tools and reliability simulator. The tradeoff between performance specs and power consumption is obtained through a multi-objective approach by considering process variations together with lifetime stress effects. The 10-bit DAC@130MS/s is herein implemented using TSMC CMOS 0.18 μm technology. Demonstrated results point out optimal design points in short and long time reliability as well as performance parameters over a computational effective procedure.

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Authors and Affiliations

  1. Faculty of Electrical Engineering, K. N. Toosi University of Technology, Tehran, Iran

    Nahid Mirzaie & Hossein Shamsi

  2. Lyle Department of Electrical Engineering, Southern Methodist University, Dallas, TX, USA

    Nahid Mirzaie & Gyung-Su Byun

Authors
  1. Nahid Mirzaie
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  2. Hossein Shamsi
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  3. Gyung-Su Byun
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Correspondence to Hossein Shamsi.

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Mirzaie, N., Shamsi, H. & Byun, GS. Resilient design of current steering DACs using a transistor level approach. Analog Integr Circ Sig Process 90, 29–41 (2017). https://doi.org/10.1007/s10470-016-0859-1

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  • DOI: https://doi.org/10.1007/s10470-016-0859-1

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