Skip to main content

Advertisement

SpringerLink
Log in

A 0.03 mm2 delta-sigma modulator with cascaded-inverter amplifier

  • Mixed Signal Letter
  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

A single stage inverter is introduced as a replacement for the conventional OTA to implement an inverter-based delta-sigma modulator. It achieves a high power and area efficiency. However, the low DC-gain and gain-bandwidth (GBW) have limited the application. This paper proposes a cascaded-inverter to increase the DC-gain and GBW, while maintaining the advantages of power and area efficiency. By cascading three inverters, the DC-gain is increased from 44 dB to 82 dB, and the GBW is increased from 100 MHz to 697 MHz. A third-order delta-sigma modulator using the proposed cascaded-inverter has been fabricated in a 0.11-μm CMOS process. When operating from a 1.2-V supply and clocked at 80 MHz, the prototype modulator achieves 59.4-dB peak SNDR over 500-kHz signal bandwidth while consuming 249 μW. Measurement results demonstrate that the application of the inverter-based amplifier, which is becoming popular due to its high power efficiency, can be extended to significantly higher speed circuits

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

References

  1. Chae, Y., & Han, G. (Feb. 2009). Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator. IEEE Journal of Solid-State Circuits, 44(2), 458–472.

  2. van Veldhoven, R. H. M., Rutten, R., & Breems, L. J. (Feb. 2008). “An inverter-based hybrid \(\Sigma \Delta\) modulator”. ISSCC digest of technical papers (pp. 492–493). San Francisco: Morgan Kaufmann Publishers.

  3. Luo, H., Han, Y., Liu, X., Liang, G., & Liao, L. (2011). “An audio cascaded \(\Sigma \Delta\) modulator using gain-boost class-C inverter.” In Proceeding of EDSSC, (pp. 1–2) Nov 2011.

  4. Chae, Y., Cheon, J., Lim, S., Kwon, M., Yoo, K., Jung, W., et al. (Jan. 2011). A 2.1 M pixels, 120 frame/s CMOS image sensor with column-parallel \(\rm \Delta \Sigma\) ADC architecture. IEEE Journal of Solid-State Circuits, 46(1), 236–247.

  5. Christen, T. (2012). A 15bit 140 \(\mu\)W scalable-bandwidth inverter-based audio \(\Delta \Sigma\) modulator with \(>\)78 dB PSRR. In Proceeding of ESSCIRC, (pp. 209–212) Sep 2012.

  6. Michel, F., & Steyaert, M. S. J. (Mar. 2012). A 250 mV 7.5 \(\mu\)W 61 dB SNDR SC \(\rm\Delta \Sigma\) modulator using near-threshold-voltage-biased inverter amplifiers in 130 nm CMOS. IEEE Journal of Solid-State Circuits, 47(3), 709–721.

  7. Roh, J. (Feb. 2006). High-gain class-AB OTA with low quiescent current. Analog Integrated Circuits and Signal Processing, 47(2), 225–228.

  8. Guo, S., & Lee, H. (Oct. 2009). Single-capacitor active-feedback compensation for small-capacitive-load three-stage amplifiers. IEEE Transactions on Circuits and Systems-II, 56(10), 758–762.

  9. Schreier, R., & Temes, G. C. (2005). Understanding delta-sigma data converters (pp. 292–294). Piscataway, NJ: IEEE Press.

    Google Scholar 

  10. Silva, J., Moon, U., Steensgaard, J., & Temes, G. C. (Jun. 2001). Wideband low-distortion delta-sigma ADC topology. Electronics Letters, 37(12), 737–738.

  11. Roh, J., Byun, S., Choi, Y., Roh, H., Kim, Y., & Kwon, J. (Feb. 2008). A 0.9-V 60-\(\mu\)W 1-bit fourth-order delta-sigma modulator with 83-dB dynamic range. IEEE Journal of Solid-State Circuits, 43(2), 361–370.

  12. Fontaine, P., Mohieldin, A. N., & Bellaouar, A. (Feb. 2005). “low-noise low-voltage CT \(\Delta \Sigma\) modulator with digital compensation of excess loop delay”. ISSCC digest of technical papers (pp. 498–499). San Francisco: Morgan Kaufmann Publishers.

  13. Nagai, T., Satou, H., Yamazaki, H., & Watanabe, Y. (Feb. 2005). “A 1.2V 3.5mW \(\Delta \Sigma\) modulator with a passive current summing network and a variable gain function”. In ISSCC digest of technical papers (pp. 494–495). San Francisco: Morgan Kaufmann Publishers.

  14. Tsang, C. W., Chiu, Y., & Nikolic, B. (2006). “A 1.2V, 10.8mW, 500kHz sigma-delta modulator with 84dB SNDR and 96dB SFDR”. In Symposium on VLSI Circuits (pp. 162–163). Honolulu: IEEE.

  15. Putter, B. (2007). “A \(5^{th}\)-order CT/DT multi-mode \(\Delta \Sigma\) modulator”. In ISSCC digest of technical papers, (pp. 244–245).

  16. Ke, Y., Gao, P., Craninckx, J., Van der Plas, G., & Gielen, G. (2010). “A 2.8-to-8.5mW GSM/Bluetooth/UMTS/DVB-H/WLAN fully reconfigurable CT \(\Delta \Sigma\) with 200kHz to 20MHz BW for 4G radios in 90nm digital CMOS”. In Symposium on VLSI Circuits (pp. 153–154) Jun 2010.

  17. Crombez, P., Van der Plas, G., Steyaert, M. S. J., & Craninckx, J. (Jun. 2010). A single-bit 500 kHz-10 MHz multimode power-performance scalable 83-to-67 dB DR CT\(\rm\Delta \Sigma\) for SDR in 90 nm digital CMOS. IEEE Journal of Solid-State Circuits, 45(6), 1159–1171.

Download references

Acknowledgments

This research was supported in part by the MSIP (Ministry of Science, ICT and Future Planning), Korea,under the ITRC (Information Technology Research Center) support program (NIPA-2014-H0301-14-1007) supervised by the NIPA (National IT Industry Promotion Agency), and supported in part by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (no. NRF-2013R1A1A2011973).

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Hanyang University, Ansan, 426-791, Korea

    Zhidong Wang, Quanzhen Duan & Jeongjin Roh

Authors
  1. Zhidong Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Quanzhen Duan
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Jeongjin Roh
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Jeongjin Roh.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Wang, Z., Duan, Q. & Roh, J. A 0.03 mm2 delta-sigma modulator with cascaded-inverter amplifier. Analog Integr Circ Sig Process 81, 495–501 (2014). https://doi.org/10.1007/s10470-014-0408-8

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-014-0408-8

Keywords

Search

Navigation