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A CMOS Image Processing Sensor for the Detection of Image Features

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Abstract

A compact CMOS vision sensor for the detection of higher level image features, such as corners, junctions (T-, X-, Y-type) and linestops, is presented. The on-chip detection of these features significantly reduces the data amount and hence facilitates the subsequent processing of pattern recognition. The sensor performs a series of template matching operations in an analog/digital mixed mode for various kinds of image filtering operations including thinning, orientation decomposition, error correction, set operations, and others. The analog operations are done in the current domain. A design procedure, based on the formulation of the transistor mismatch, is applied to fulfill both accuracy and speed requirements. The architecture resembles a CNN-UM that can be programmed by a 30-bit word. The results of an experimental 16 × 16 pixel chip demonstrate that the sensor is able to detect features at high speed due to the pixel-parallel operation. Over 270 individual processing operations are performed in about 54 μsec.

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References

  1. C. Mead, Analog VLSI and Neural Systems. Addison Wesley, Reading, MA, 1989.

    Google Scholar 

  2. D. Standley, “An object position and orientation IC with embedded imager.” IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 1853–1859, 1991.

    Article  Google Scholar 

  3. P. Venier, A. Mortara, X. Arreguit, and E. Vittoz, “An integrated cortical layer for orientation enhancement.” IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 177–186, 1997.

    Article  Google Scholar 

  4. M. Barbaro, P. Burg, A. Mortara, P. Nussbaum, and F. Heitger, “A 100 × 100 pixel silicon retina for gradient extraction with steering filter capabilities and temporal output coding.” IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 160–172, 2002.

    Article  Google Scholar 

  5. R. Etienne-Cummings, Z. Kalayjian, and D. Cai, “A programmable focal-plane MIMD image processor chip.” IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 64–73, 2001.

    Article  Google Scholar 

  6. T. Bernard, B. Zavidovique, and F. Devos, “A programmable artificial retina.” IEEE J. Solid-State Circuits, vol. 28, no. 7, pp. 789–798, 1993.

    Article  Google Scholar 

  7. J. Eklund, C. Svensson, and A. Åström, “VLSI implementation of a focal plane image processor—A realization of the near-sensor image processing chip concept.” IEEE Trans. VLSI Systems, vol. 4, no. 3, pp. 322–335, 1996.

    Article  Google Scholar 

  8. M. Ishikawa, K. Ogawa, T. Komuro, and I. Ishii, “A CMOS vision chip with SIMD processing element array for 1ms image processing,” in Technical Digest of the International Solid-State Circuits Conference, 1999, pp. 206–207.

  9. L. Chua and T. Roska, “Cellular neural networks: Theory.” IEEE Trans. Circuits Syst., vol. 35, pp. 1257–1272, 1988.

    Article  Google Scholar 

  10. S. Espejo, A. Rodrigues-Vazquez, R. Domínguez-Castro, J. Huetas, and E. Sanchez-Sinencio, “Smart-pixel cellular neural networks in analog current-mode CMOS technology.” IEEE J. Solid-State Circuits, vol. 29, no. 8, pp. 895–905, 1994.

    Article  Google Scholar 

  11. P. Kinget and M. Steyaert, “A programmable analog cellular neural network CMOS chip for high speed image processing.” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 235–243, 1995.

    Article  Google Scholar 

  12. L. Chua and T. Roska, “The CNN universal machine, part 1: The architecture,” in Proc. Second IEEE Int. Workshop Cellular Neural Networks and Their Applicat., 1992, pp. 1–10.

  13. R. Domínguez-Castro, S. Espejo, A. Rodríguez-Vázquez, R. Carmona, P. Földesy, Á. Zarándy, P. Szolgay, T. Szirányi, and T. Roska, “A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instruction storage.” IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1013–1025, 1997.

    Article  Google Scholar 

  14. F. Attneave, “Some informational aspects of visual perception.” Psychological Review, vol. 61, no. 3, pp. 183–193, 1954.

    PubMed  Google Scholar 

  15. M. Nishimura, “A VLSI computational sensor for the detection of image features.” Ph. D. dissertation, University of Pennsylvania, Philadelphia, PA, 2001.

  16. K. Lakshmikumar, R. Hadaway, and M. Copeland, “Characterization and modeling of mismatch in MOS transistors for precision analog design.” IEEE J. Solid-State Circuits, vol. 21, no. 6, pp. 1057–1066, 1986.

    Article  Google Scholar 

  17. M. Pelgrom, “Matching properties of MOS transistors.” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433–1440, 1989.

    Article  Google Scholar 

  18. P. Kinget and M. Steyaert, Analog VLSI Integration of Massively Parallel Processing Systems. Kluwer Academic Publishers, 1996.

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Authors and Affiliations

  1. Sankyo Co, Ltd, 1-2-58, Hiromachi 1-Chome, Shinagawa-K, Tokyo, Japan

    Masatoshi Nishimura

  2. Department of Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, PA, USA

    Jan Van der Spiegel

Authors
  1. Masatoshi Nishimura
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  2. Jan Van der Spiegel
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Masatoshi Nishimura was born in 1962 in Japan. He received his B.S. degree in mathematical engineering and information physics from the University of Tokyo in 1984. In 2001 he received his Ph.D. in Electrical Engineering from the University of Pennsylvania. His Ph.D. research focused on biologically inspired algorithms for the feature detection in visual images. Except for the three years he spent at University of Pennsylvania, he has been working for Sankyo since 1984, where he has been involved in the research and development of medical instruments including a microchip for capillary electrophoresis. He is currently working in the field of bioinformatics.

Jan Van der Spiegel received his Masters and Ph.D. degrees in Electrical Engineering from the University of Leuven, Belgium, in 1974 and 1979, respectively. He joined the University of Pennsylvania in 1981 where he is currently a Professor of Electrical and Systems Engineering and the director of the Center for Sensor Technologies. He was the chairman of the Department of Electrical Engineering from 1998 to 2002 and the interim chairman of the Electrical and Systems Engineering department at the University of Pennsylvania from 2002 to 2004. His research interests are in mixed-mode VLSI design, biologically based sensors and sensory information processing systems, micro-sensor technology, and analog-to-digital converters. He is the author of over 150 journal and conference papers and holds 4 patents. He is a Fellow of the IEEE (2002) and the recipient of the IEEE Third Millennium Medal, the UPS Foundation Distinguished Education Chair and the Bicentennial Class of 1940 Term Chair. He received the Christian and Mary Lindback Foundation, and the S. Reid Warren Award for Distinguished Teaching. He was also Editor of Sensors and Actuators A for North and South America from 1983 to 2004.

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Nishimura, M., Van der Spiegel, J. A CMOS Image Processing Sensor for the Detection of Image Features. Analog Integr Circ Sig Process 45, 263–279 (2005). https://doi.org/10.1007/s10470-005-4955-x

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  • DOI: https://doi.org/10.1007/s10470-005-4955-x

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