Skip to main content
SpringerLink
Log in

Effects of non-uniform doping on junctionless transistor

  • Published:
Applied Physics A Aims and scope Submit manuscript

Abstract

In this paper, we study the effects of non-uniform channel doping on junctionless transistor (JLT) using 3D quantum simulations. The JLT devices require a uniformly doped ultrathin channel. Although we take uniform doping for study, in practice, it will be technologically difficult to obtain. For technological reason, after thermal annealing, the impurity profile in semiconductor device becomes uniform along lateral channel direction and non-uniform along vertical direction. Here, we show that this directly affects the short channel behaviour and reduces on-current.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

References

  1. J.-P. Colinge, C.-W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, R. Murphy, Nanowire transistors without junctions. Nat. Nanotechnol. 5(3), 225–229 (2010)

    Article  ADS  Google Scholar 

  2. C.-J. Su, T.-I. Tsai, Y.-L. Liou, Z.-M. Lin, H.-C. Lin, T.-S. Chao, Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels. IEEE Electron. Device Lett. 32(4), 521–523 (2011)

    Article  ADS  Google Scholar 

  3. C. Chen, J. Lin, M. Chiang, K. Kim, High performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application, in Proceeding of the IEEE International SOI Conference, 2010, pp. 1–2

  4. C.-W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, J. Colinge, Junctionless multigate field-effect transistor. Appl. Phys. Lett. 94(5), 053511–053512 (2009)

    Article  ADS  Google Scholar 

  5. J.P. Colinge, C.-W. Lee, I. Ferain, N.D. Akhavan, R. Yan, R. Razavi, R. Yu, A.N. Nazarov, R.T. Doria, Reduced electric field in junctionless transistors. Appl. Phys. Lett. 96(7), 073510-1–073510-3 (2010)

    Article  ADS  Google Scholar 

  6. C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N.D. Akhavan, P. Razavi, J.-P. Colinge, Performance estimation of junctionless multigate transistors. Solid State Electron 54(2), 97–103 (2010)

    Article  ADS  Google Scholar 

  7. S. Gundapaneni, S. Ganguly, A. Kottantharayil, Bulk planar junctionless transistor (BPJLT): an attractive device alternative for scaling. IEEE Electron Device Lett. 32(3), 261–263 (2011)

    Article  ADS  Google Scholar 

  8. S.-J. Choi, D.-I. Moon, S. Kim, J. Duarte, Y.-K. Choi, Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Lett. 32(2), 125–127 (2011)

    Article  ADS  Google Scholar 

  9. R. Rios, A. Cappellani, M. Armstrong, A. Budrevich, H. Gomez, R. Pai, N. Rahhal-orabi, K. Kuhn, Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm. IEEE Electron Device Lett. 32(9), 1170–1172 (2011). doi:10.1109/LED.2011.2158978

    Article  ADS  Google Scholar 

  10. S.M. Sze, Physics of Semiconductor Devices, 2nd edn. (Wiley, New York, 1983)

    Google Scholar 

  11. K. Suzuki, Y. Kataoka, S. Nagayama, C.W. Magee, T.H. Buyuklimanli, T. Nagayama, Analytical model for redistribution profile of ion implanted impurities during solid-phase epitaxy. IEEE Trans. Electron Devices 54(2), 262–271 (2007)

    Article  ADS  Google Scholar 

  12. S. Jeon, S. Park, Tunable work-function engineering of TiC-TiN compound by atomic layer deposition for metal gate applications. J. Electrochem. Soc. 157(10), H930–H933 (2010)

    Article  Google Scholar 

  13. P. Ranade, R. Lin, Q. Lu, Y.-C. Yeo, H. Takeuchi, T.-J. King, C. Hu, Molybdenum gate electrode technology for deep sub-micron CMOS generations, in Proceedings of the Material Research Society Symposium. Gate Stack Silicide Issues Silicon Process II, vol. 670 (Pittsburgh, PA: Mater. Res. Soc., 2002). pp. K5.2.1–K5.2.6

  14. Silvaco, Version 5.16.3.R. (2010) [Online]. Available: http://www.silvaco.com

  15. M.-H. Han, C.-Y. Chang, H.-B. Chen, J.-J. Wu, Y.-C. Cheng, Y.-C. Wu, Performance comparison between bulk and SOI junctionless transistors. Electron Device Lett. 34(2), 69–171 (2013)

    ADS  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, 208016, India

    Partha Mondal, Bahniman Ghosh, Punyasloka Bal, M. W. Akram & Akshaykumar Salimath

  2. Microelectronics Research Center, University of Texas at Austin, 10100 Burnet Road, Austin, TX, 78758, USA

    Bahniman Ghosh

Authors
  1. Partha Mondal
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Bahniman Ghosh
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Punyasloka Bal
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. M. W. Akram
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Akshaykumar Salimath
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Akshaykumar Salimath.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Mondal, P., Ghosh, B., Bal, P. et al. Effects of non-uniform doping on junctionless transistor. Appl. Phys. A 119, 127–132 (2015). https://doi.org/10.1007/s00339-015-9026-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00339-015-9026-2

Keywords

Search

Navigation