Abstract
There is wide agreement that one of the most significant impediments to the performance of current and future pipelined superscalar processors is the presence of conditional branches in the instruction stream. Speculative execution is one solution to the branch problem, but speculative work is discarded if a branch is mispredicted. For it to be effective, speculative execution requires a very accurate branch predictor; 95% accuracy is not good enough. This paper proposes branch classification, a methodology for building more accurate branch predictors. Branch classification allows an individual branch instruction to be associated with the branch predictor best suited to predict its direction. Using this approach, a hybrid branch predictor can be constructed such that each component branch predictor predicts those branches for which it is best suited. To demonstrate the usefulness of branch classification, an example classification scheme is given and a new hybrid predictor is built based on this scheme which achieves a higher prediction accuracy than any branch predictor previously reported in the literature.
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References
P. M. Kogge, The Architecture of Pipelined Computers, McGraw-Hill, pp. 237–243, (1981).
S. McFarling, Combining branch predictors, WRL Technical Note TN-36, Digital Equipment Corporation, June 1993.
P. Chow and M. Horowitz, Architecture tradeoffs in the design of MIPS-X, Proc. of the 14th Ann. Int. Symp. on Computer Architecture, pp. 300–308 (June 1987).
C. Melear, The design of the 88000 RISC family, IEEE MICRO, pp. 26–38 (April 1989).
J. Emer and D. Clark, A characterization of processor performance in the VAX-11/780, Proc. of the 11th Ann. Symp. on Computer Architecture, pp. 301–310 (June 1984).
J. F. K. Lee and A. J. Smith, Branch prediction strategies and branch target buffer design, IEEE Computer, pp. 6–22 (January 1984).
J. E. Smith, A study of branch prediction strategies, Proc. of the eighth Int. Symp. on Computer Architecture, pp. 135–148 (June 1981).
J. A. Fisher and S. M. Freudenberger, Predicting conditional branch directions from previous runs of a program, Proc. of the fifth Int. Conf. on Architectural Support for Programming Languages and Operating Systems, pp. 85–95 (1992).
J. A. DeRosa and H. M. Levy, An evaluation of branch architectures, Proc. of the 14th Int. Symp. on Computer Architecture, pp. 10–16 (June 1987).
S. McFarling and J. L. Hennessey, Reducing the cost of branches, Proc. of the 13th Int. Symp. on Computer Architecture, pp. 396–404 (June 1986).
T.-Y. Yeh and Y. N. Patt, Alternative implementations of two-level adaptive branch prediction, Proc. of the 19th Ann. Int. Symp. on Computer Architecture, pp. 124–135 (May 1992).
T.-Y. Yeh and Y. N. Patt, Two-level adaptive branch prediction, Proc. of the 24th ACM/IEEE Int. Symp. on Microarchitecture, pp. 51–61 (November 1991).
T.-Y. Yeh and Y. N. Patt, A comparison of dynamic branch predictors that use two levels of branch history, Proc. of the 20th Ann. Int. Symp. on Computer Architecture, pp. 257–266 (May 1993).
D. W. Hammerstrom and E. S. Davidson, Information content of CPU memory referencing behavior, Proc. of the 15th Ann. Workshop on Microprogramming, pp. 85–95 (October 1982).
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Chang, PY., Hao, E., Yeh, TY. et al. Branch Classification: A New Mechanism for Improving Branch Predictor Performance. Int J Parallel Prog 24, 133–158 (1996). https://doi.org/10.1007/BF03356745
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DOI: https://doi.org/10.1007/BF03356745