Abstract
We present three explicit schemes for distributingM variables amongN memory modules, whereM=Θ(N 1.5),M = Θ(N 2), andM=Θ(N 3), respectively. Each variable is replicated into a constant number of copies stored in distinct modules. We show thatN processors, directly accessing the memories through a complete interconnection, can read/write any set ofN variables in worst-case timeO (N 1/3),O(N 1/2), andO(N 2/3), respectively for the three schemes. The access times for the last two schemes are optimal with respect to the particular redundancy values used by such schemes. The address computation can be carried out efficiently by each processor without recourse to a complete memory map and requiring onlyO(1) internal storage.
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This paper was partially supported by NFS Grants CCR-91-96152 and CCR-94-00232, by ONR Contract N00014-91-J-4052, ARPA Order 8225, and by the ESPRIT III Basic Research Programme of the EC under Contract No. 9072 (Project GEPPCOM). Results reported here were presented in preliminary form at the 10th Symposium on Theoretical Aspects of Computer Science (Würzburg, Germany, 1993), and at the 5th ACM Symposium on Parallel Algorithms and Architectures (Velen, Germany, 1993).
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Pietracaprina, A., Preparata, F.P. Practical constructive schemes for deterministic shared-memory access. Theory of Computing Systems 30, 3–37 (1997). https://doi.org/10.1007/BF02679451
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DOI: https://doi.org/10.1007/BF02679451