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Interface trap and interface depletion in lattice-mismatched GaInAs/GaAs heterostructures

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Abstract

The effects of lattice mismatch on the deep traps and interface depletion have been studied for the Ga0.92In0.08As(p+)/GaAs(N) and Ga0.92In0.08As(n)/GaAs(SI) heterostructures grown by molecular beam epitaxy. We have used deep level transient spectroscopy (DLTS) and admittance spectroscopy (AS) and observed two hole traps, one at an energy ranging from 0.1 to 0.4 eV and the other at 0.64 eV, and two electron traps at 0.49 and 0.83 eV in the GalnAs/GaAsp +-N junction sample. The hole trap appeared as a broad peak in the DLTS data and its energy distribution (0.1 ∼ 0.4 eV) was obtained by a simulation fitting of the peak. Concentration of this distributed hole trap increased as the in-plane mismatch increased, suggesting its relation to defects induced by lattice relaxation, whereas the other traps are from the bulk. The misfit dislocations are believed to be responsible for the interface trap. For the Ga0.92In0.08As(n)/GaAs(SI) samples, Hall effect measurements showed an increased interface depletion width of about 0.14 Μm for the 0.5 Μm thick layer and about 0.12 /gmm for the 0.25 Μm thick layer, while a corresponding GaAs/GaAs sample had only 0.088 Μm for the interface depletion width.

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Choi, Y.W., Xie, K., Kim, H.M. et al. Interface trap and interface depletion in lattice-mismatched GaInAs/GaAs heterostructures. J. Electron. Mater. 20, 545–551 (1991). https://doi.org/10.1007/BF02666016

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  • DOI: https://doi.org/10.1007/BF02666016

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