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Temporal logic based hardware description and its verification with Prolog

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Abstract

Techniques of hierarchical specification and verification of hardware with temporal logic and Prolog are presented by example. Both hardware designs in gates and state-diagrams are translated into a relation between the present and the next state, which is represented in Prolog.1) Specifications are constructed by temporal logic that can express state sequences (e.g. timing diagrams) easily and also are translated into a relation between the present and the next state in Prolog.

The verification method is based upon the temporal logic decision procedure in Ref. 2) and, referring to the relation tables between the present state and the next state, the verifier can reason in both directions—forward and backward in temporal sequences. Prolog has very powerful pattern matching, and its automatic backtracking capabilities facilitate easy-to-write verifier programs.

It is concluded that a total verification system handling various design levels can be constructed with temporal logic and Prolog.

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References

  1. Fujita, M., Tanaka, H., and Moto-oka, T.: “Verification with Prolog and Temporal Logic”, 6th Computer Hardware Description Languages and their Applications (May, 1983).

  2. Wolper, P.: “Temporal Logic Can Be More Expressive”, 22nd Annual Symposium on Foundation of Computer Science (October, 1981).

  3. Pitchuman, V., and Stabler, E. P.: “A Formal Method for Computer Design Verification”, 19th Design Automation Conference (1982).

  4. Darringer, J. A.: “The Application of Program Verification Technique to Hardware Verification”, 16th Design Automation Conference (1979).

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  8. Uehara, T., Saito, T., Maruyama, F., and Kawato, N.: “DDL Verifier and Temporal Logic”, 6th Computer Hardware Description Languages and their Applications (May, 1983).

  9. Clarke, E. M., Emerson, E. A., and Sistla, A. P.: “Automatic Verification of Finite State Concurrent System Using Temporal Logic Specification: A Practical Approach”, Principles of Programming Language (1983).

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Authors and Affiliations

  1. Department of Electrical Engineering, Faculty of Engineering, The University of Tokyo, 3-1 Hongo 7-chome, Bunkyo-ku, 113, Tokyo, Japan

    Masahiro Fujita, Hidehiko Tanaka & Tohru Moto-Oka

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  1. Masahiro Fujita
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  2. Hidehiko Tanaka
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  3. Tohru Moto-Oka
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Fujita, M., Tanaka, H. & Moto-Oka, T. Temporal logic based hardware description and its verification with Prolog. New Gener Comput 1, 195–203 (1983). https://doi.org/10.1007/BF03037426

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  • DOI: https://doi.org/10.1007/BF03037426

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