Abstract
As developed by Wallace and Dadda, a method for high-speed, parallel multiplication is to generate a matrix of partial products and then reduce the partial products to two numbers whose sum is equal to the final product. The resulting two numbers are then summed using a fast carry-propagate adder. This paper presents Reduced Area multipliers, which employ a modified reduction scheme that results in fewer components and less interconnect overhead than either Wallace or Dadda multipliers. This reduction scheme is especially useful for pipelined multipliers, because it minimizes the number of latches required in the reduction of the partial products. The reduction scheme can be applied to either unsigned (sign-magnitude) or two's complement numbers. Equations are given for determining the number of components and a method is presented for estimating the interconnect overhead for Wallace, Dadda, and Reduced Area multipliers. Area estimates indicate that for non-pipelined multipliers, the reduction in area achieved with Reduced Area multipliers ranges from 3.7 to 6.6 percent relative to Dadda multipliers, and from 3.8 to 8.4 percent relative to Wallace multipliers. For fully pipelined multipliers, the reduction in area ranges from 15.1 to 33.6 percent relative to Dadda multipliers, and from 2.9 to 9.0 percent relative to Wallace multipliers.
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Bickerstaff, K.C., Schulte, M.J. & Swartzlander, E.E. Parallel reduced area multipliers. Journal of VLSI Signal Processing 9, 181–191 (1995). https://doi.org/10.1007/BF02407084
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DOI: https://doi.org/10.1007/BF02407084