Abstract
Presented is a register structure and generator design which enables non-scan sequential testing using parallel pseudorandom-based patterns applied to the circuit's primary inputs. The proposed register structure and register control strategy uses the circuit under test's (CUT's) natural sequential activity to periodically alter a register's output bias to a value near 0.5 (i.e. alter the spread of 1's in the output stream). Thus, over time, it is possible to introduce a larger spread circuit states than that normally reachable when parallel pseudorandom-based test patterns are applied to the input lines of a CUT. Using the register modification, a simple hardware generation system can be designed and is suitable for both on-chip and external testing. Experiments indicate that high fault coverage is attainable in a relatively short test time.
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References
M. Abromovici, K. Rajan, and D. Miller, “FREEZE: A New Approach for Testing Sequential Circuits,”Proc. 29th Design Automation Conference, pp. 22–25, 1992.
P.H. Bardell, W.H. McAnney, and J. Savir,Built-In Self-Test for VLSI, Wiley-Interscience, New York, 1987.
F. Brglez, D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits,”Proc. Intl. Symposium on Circuits & Systems, pp. 1929–1934, 1989.
F. Brglez, C. Gloster, and G. Kedem, “Hardware-Based Weighted random Pattern Generation for Boundary Scan,”Proc. Intl. Test Conference, pp. 264–274, 1989.
V. Chikermane, E.M. Rudnick, P. Banerjee, and J.H. Patel, “Non-Scan Design for Testability Techniques for Sequential Circuits,”Proc. 30th Design Automation Conference, pp. 236–24, June 1993.
E.B. Eichelberger and T.W. Williams, “A Logic Design Structure for LSI Testability,”Journal Design Automat. Fault Tolerant Comp., Vol. 2, pp. 165–178, May 1978.
P.D. Hortensius, et al., “Celluar Automata-Based Pseudorandom Number Generators for Built-In Self-Test,”Third Technical Workshop—New Directions for IC Testing, pp. 117–128, Halifax, October, 1988.
A. Krasniewski and S. Pilarski, “Circular Self-Test Path: A Low-Cost BIST Technique,”Proc. 24th Design Automation Conference, pp. 407–415, 1987.
A. Lioy, P.L. Montessoro, and S. Gai, “A Complexity Analysis of Sequential ATPG,”Proc. Intl. Symposium on Circuits & Systems, pp. 1946–1949, 1989.
F. Muradali, V.K. Agarwal, and B. Nadeau-Dostie, “A New Procedure for Weighted Random Buit-In Self-Test,”Proc. Intl. Test Conference, pp. 660–669, 1990.
B. Nadeau-Dostie, D. Burek, and A.S. Hassan, “ScanBist: A Multi-Frequency Scan-Based BIST Method,”Proc. Intl. Test Conference, pp. 506–513, 1992.
T.W. Williams and K.P. Parker, “Design for Testibility—A Survey,”Proc. IEEE, Vol. 71, pp. 98–112, January 1983.
H-J Wunderlich, “Multiple Distributions for Basee Random Test Patterns,”Proc. Intl. Test Conference, pp. 236–244, 1988.
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Muradali, F., Nishida, T. & Shimizu, T. A structure and technique for pseudorandom-based testing of sequential circuits. J Electron Test 6, 107–115 (1995). https://doi.org/10.1007/BF00993133
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DOI: https://doi.org/10.1007/BF00993133