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Reducing the CMOS RAM test complexity withI DDQ and voltage testing

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Abstract

In this article, we outline a RAM test methodology taking into accountI DDQ and voltage based March tests. RAM test cost forms a significantly large portion of its total production cost and is projected to increase even further for future RAM generations.I DDQ testing can be utilized to reduce this cost. However, owing to architectural and operational constrains of RAMs, a straight forward application ofI DDQ testing has very limited defect detection capability. These constrains are removed by creating anI DDQ test mode in RAMs. All bridging defects in RAM matrix, including the gate oxide defects, are detected by fourI DDQ measurements. TheI DDQ test is then supplemented with voltage based March test to detect the defects (opens, data retention) that are not detectable usingI DDQ technique. The combined test methodology reduces the algorithmic test complexity for a given SRAM fault model from 16n to 5n+4I DDQ measurements.

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  1. Philips Research Laboratories, P.O. Box 80000, 5600 JA, Eindhoven, The Netherlands

    Manoj Sachdev

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  1. Manoj Sachdev
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Sachdev, M. Reducing the CMOS RAM test complexity withI DDQ and voltage testing. J Electron Test 6, 191–202 (1995). https://doi.org/10.1007/BF00993086

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  • DOI: https://doi.org/10.1007/BF00993086

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