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VLSI parallel architecture for Kalman filterAn algorithm specific approach

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Abstract

An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are performed in parallel which leads to a speedup of about 40%. Throughput has been increased by using bi-trapezoidal arrays. Techniques have been employed for data storage and skewing which enables fast data transfer rates. A VLSI implementation of a prototype of matrix of size 4×4 has been discussed.

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Authors and Affiliations

  1. The Center of Advanced Computer Studies, University of Southwestern Louisiana, 70504, Lafayette, Louisiana

    Magdy A. Bayoumi

  2. Cirrus Logic, 3100 West Warren Ave., 94538, Fremont, CA

    Padma Rao

  3. The Center of Advanced Computer Studies, University of Southwestern Louisiana, 70504, Lafayette, Louisiana

    Bassem Alhalabi

Authors
  1. Magdy A. Bayoumi
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  2. Padma Rao
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  3. Bassem Alhalabi
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Bayoumi, M.A., Rao, P. & Alhalabi, B. VLSI parallel architecture for Kalman filterAn algorithm specific approach . J VLSI Sign Process Syst Sign Image Video Technol 4, 147–163 (1992). https://doi.org/10.1007/BF00925119

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  • DOI: https://doi.org/10.1007/BF00925119

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