Abstract
Nowadays, users need portable gadgets like laptops and cellular phones with small in size which occupies less area, consumes low power and having low cost. Justifying Moore’s law by designing the smaller size transistors on the silicon wafer, more numbers of transistors available on a single wafer help to design complicated circuits with very low cost. Scaling plays vital role to decide the size of transistor with high performance. Most attracted multi-gate technology for researchers as well for industry is Fin-FET for nano-scale design. The nano-scale Fin-FET technology provides best solution for Moore’s law. This paper focuses on how Fin-FET helps to reduce short channel effect and also presents design of 30 nm and 10 nm single Fin-FET with Triple Gate. Leakage current, threshold voltage and drain drive current evaluated from device design by using high K of dielectric material. Simulation carried out using COMSOL MULTIPHYSICS Version 5.3
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I thankfully acknowledge Ni2 Logic Design, Pune, for providing the licensed tool for implementation of Fin-FET fdesigns.
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Jagtap, S.M., Gond, V.J. (2021). “Device Design of 30 and 10 nm Triple Gate Single Finger Fin-FET for on Current (ION) and off Current (IOFF) Measurement”. In: Satapathy, S.C., Bhateja, V., Favorskaya, M.N., Adilakshmi, T. (eds) Smart Computing Techniques and Applications. Smart Innovation, Systems and Technologies, vol 224. Springer, Singapore. https://doi.org/10.1007/978-981-16-1502-3_80
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