Abstract
Over the years semiconductor design complexities have increased to multi million gates. With increase in design sizes, power consumption saving has become a key challenge. The power consumption in test modes is found to be higher, as all the logic blocks are used simultaneously. Some techniques to save test mode power during shift and capture cycles are already in use. But the existing techniques are not deterministic and does not provide user control mechanism. This paper proposes a mechanism called Shift Power Chain (SPC) to deterministically control and reduce shift power in test compression mode. Our mechanism provides significant reduction in peak and average shift power. We present the experimental results on large scale industrial designs as well as ISCAS’89 and Opencore benchmarks.
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Basu, K., Kumar, R., Kulkarni, S., Kapur, R. (2017). Deterministic Shift Power Reduction in Test Compression. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_17
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DOI: https://doi.org/10.1007/978-981-10-7470-7_17
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