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Advanced Techniques in Computing Sciences and Software Engineering pp 191–196Cite as

Studies on SEE Characteristic and Hardening Techniques of CMOS SRAM with Sub-micro Feature Sizes

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Abstract

The single event effects (SEE) characteristic and hardening techniques of CMOS SRAM with sub-micron feature size are studied in the paper. After introducing the relationship SEE with the structure of memory cell, the rate of read-write, the feature sizes and the power supply, the SEE hardening techniques for the COMS SRAM are given from tow aspect: device-level hardening techniques and system-level hardening techniques. Finally, an error detection and correction (EDAC) design based on high reliability anti-fused FPGA is presented, this design has special real-time performance and high reliability, and has been adopted in a space-bone integrated processor platform, which works well in all kinds of environmental experiments.

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Authors and Affiliations

  1. ATR Key Lab, National University of Defense Technology, Changsha, 410073, China

    He Xing-hua, Zhang Cong, Zhang Yong-liang & Lu Huan-zhang

Authors
  1. He Xing-hua
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  2. Zhang Cong
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  3. Zhang Yong-liang
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  4. Lu Huan-zhang
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Corresponding author

Correspondence to He Xing-hua .

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Editors and Affiliations

  1. School of Engineering, University of Bridgeport, University Avenue 221, Bridgeport, 06604, U.S.A.

    Khaled Elleithy

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Xing-hua, H., Cong, Z., Yong-liang, Z., Huan-zhang, L. (2010). Studies on SEE Characteristic and Hardening Techniques of CMOS SRAM with Sub-micro Feature Sizes. In: Elleithy, K. (eds) Advanced Techniques in Computing Sciences and Software Engineering. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3660-5_33

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  • DOI: https://doi.org/10.1007/978-90-481-3660-5_33

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  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-90-481-3659-9

  • Online ISBN: 978-90-481-3660-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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