Abstract
Aggressive device scaling down to the nano-meter range offers IC designers both opportunities and challenges. Digital designers benefit greatly from the system flexibility and affordability, but analog/RF designers are struggling with flawed devices. Since scaled devices are faster and smaller, the incentive to use such strengths advantageously has prompted many efforts to overcome analog imperfection by digital means. Designers are introducing more DSP functionality to enhance the performance of analog/RF systems. More intelligence is being built into analog/RF designs as in linear PA, RF receiver front-end, ADC/DAC, digital PLL, etc. Such pervasive design techniques with digital assisting will prevail in the future SOC design. After a brief overview of the trend, examples of the LMS-based calibration algorithm applied to the pipeline and CT cascaded ΔΣ modulator are discussed.
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Song, BS. (2010). LMS-Based Digital Assisting for Data Converters. In: Roermund, A., Casier, H., Steyaert, M. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3083-2_1
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