Abstract
Executing complex network packet applications typically requires using network processors and parallel processing to handle packet transmission speeds of 1 gigabit per second and beyond. Heterogeneous computing approaches also employ specialized coprocessors, such as associative memory processors for flow matching and regular expression (regex) processors for packet payload searching. Our goals for this kind of heterogeneous processing are to free application developers from hardware-specific details and to develop systems in which we can deploy new hardware and software components in modular, plug-and-play fashion. Our initial contribution to realizing these goals involves (1) expressing classic packet operations in a C dialect as C/C++-style operators; (2) compiling user code into bytecodes for a packet-processing virtual machine that hides machine-specific details; and (3) interpreting the bytecodes with microcoded interpreters that orchestrate an ensemble of heterogeneous processors on the users’ behalf.
Intel is a trademark of Intel Corporation in the United States and/or other countries. Broadcom® is a registered trademark of Broadcom Corporation in the United States and/or other countries. Xilinx is a trademark of Xilinx Inc. in the United States and/or other countries. OCTEON® is a registered trademark of Cavium. AMCC is a registered trademark of Applied Micro Circuits Corporation. IDT is a trademark of Integrated Device Technology, Inc. packetC® is a registered trademark of CloudShield Technologies, Inc. in the United States and/or other countries.
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Duncan, R., Jungck, P., Ross, K., Frandeen, J., Triplett, G. (2014). Managing Heterogeneous Processor Machine Dependencies in Computer Network Applications . In: an Mey, D., et al. Euro-Par 2013: Parallel Processing Workshops. Euro-Par 2013. Lecture Notes in Computer Science, vol 8374. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-54420-0_28
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DOI: https://doi.org/10.1007/978-3-642-54420-0_28
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