Fault Aware Dynamic Adaptive Routing Using LBDR

Abstract

Network-on-Chip (NoC) is evolving as an efficient and scalable interconnect architecture for current and future CMP, MPSoC systems. An important challenge in NoC design is to choose an appropriate routing algorithm, as it impacts the NoC performance. As technology scales down to Deep-Submicron (DSM), on-chip networks are becoming increasingly prone to failures. At higher level these failures are handled by fault tolerant routing algorithms. Fault tolerant routing algorithms avoid faulty regions and route traffic through safe regions. Currently, routing algorithms are implemented as source or distributed routing. To handle faults, both source and distributed routing make use of routing tables. Algorithms implemented with routing tables do not scale well with network size. Scalable routing implementation, such as Logic Based Distributed Routing (LBDR) has been proposed for efficient and compact implementation of routing. LBDR handles faults without using routing table. In this paper we propose a fault tolerant routing scheme based on LBDR which aims to handle faults while at the same time addressing network congestion. Proposed method integrates deterministic and adaptive routing schemes to avoid congestion as well as faults that may be present in the network. Experimental results show the effectiveness of proposed method in case of single and multiple link failures.