Abstract
Network-on-Chip (NoC) has been proposed to perform high performance and scalability in System-on-Chip (SoC) design. Interconnection modeling was widely used to evaluate performance, especially for large-scale NoCs. In this paper, the router modeling for multi-transaction bus architecture on distributed system with bufferless microarchitectures was presented to analyze and evaluate the performance and model the success rate of each node respectively. It will facilitate the analysis of impact for different priorities. The accuracy of our approach and its practical use is illustrated through extensive simulation results.
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Chiu, JC., Yang, KM., Wong, CA. (2012). Analytical Modeling for Multi-transaction Bus on Distributed Systems. In: Xiang, Y., Stojmenovic, I., Apduhan, B.O., Wang, G., Nakano, K., Zomaya, A. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2012. Lecture Notes in Computer Science, vol 7440. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33065-0_1
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DOI: https://doi.org/10.1007/978-3-642-33065-0_1
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