Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects

Abstract

Most of the encoding methods proposed in recent years have dealt with only RC modeled VLSI interconnects. For deep sub-micron (DSM) technologies, the effect of on-chip inductance has increased due to increasing clock frequency, reducing signal rise times and increasing on-chip interconnect length. This issue is a concern for signal integrity and overall chip performance. Therefore, this research work introduces an efficient bus encoder using Bus Inverting (BI) method. This method considerably reduces crosstalk, delay and power dissipation in RLC modeled circuits. The proposed encoder dissipates lower power which makes it suitable for current high-speed low power VLSI interconnects. It has been observed that on an average, the proposed encoder reduces power dissipation and propagation delay by 67.86% and 46.78%, respectively.