Abstract
SystemC TLM (Transaction Level Modeling) enables the description of complex Systems on Chip (SoC) at a high level of abstraction. It offers a number of advantages regarding architecture exploration, simulation performance, and early software development. The tendency is therefore to use TLM-based descriptions of SoC platforms as golden models that, by essence, must be flawless.
In this paper, a SoC critical embedded platform under development by Astrium is used as proof-of-concept demonstrator, to assess the ISIS prototype tool which is devoted to the verification of SystemC TLM designs. Given temporal properties that capture the intended requirements, ISIS automatically instruments the design with ad hoc checkers that inform about the satisfaction of the properties during simulation.
After a description of the target platform design, we show that the PSL language enables the unambiguous expression of the required properties, and that the checkers produced by ISIS verify their satisfaction with a limited simulation time overhead.
This work is supported by the French project SoCKET (FUI).
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
IEEE Std 1666-2005, IEEE Standard System C Language Reference Manual. IEEE (2005)
IEEE Std 1800-2005, IEEE Standard for System Verilog: Unified Hardware Design, Specification and Verification Language. IEEE (2005)
IEEE Std 1850-2005, IEEE Standard for Property Specification Language (PSL). IEEE (2005)
Avinun, R.: Validate hardware/software for nextgen mobile/consumer apps using software-on-chip system development tools. EETimes (December 2010), http://www.eetimes.com/design/embedded/4211507/Validate-hardware-software-for-nextgen-mobile-consumer-apps-using-software-on-chip-system-development-tools-
Cornet, J.: Separation of Functional and Non-Functional Aspects in Transactional Level Models of Systems-on-Chip. PhD thesis, INP Grenoble (2008)
Ecker, W., Esen, V., Hull, M.: Specification Language for Transaction Level Assertions. In: Proc. HLDVT 2006 (2006)
Ecker, W., Esen, V., Hull, M.: Implementation of a Transaction Level Assertion Framework in SystemC. In: Proc. DATE 2007 (2007)
Ferro, L., Pierre, L.: Formal Semantics for PSL Modeling Layer and Application to the Verification of Transactional Models. In: Proc. DATE 2010 (March 2010)
Ferro, L., Pierre, L.: ISIS: Runtime Verification of TLM Platforms. In: Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s. LNEE, vol. 63. Springer, Heidelberg (2010)
Ghenassia, F. (ed.): Transaction-Level Modeling with SystemC. Springer, Heidelberg (2005)
Goering, R.: Transaction models offer new deal for EDA. EETimes (March 2006), http://www.eetimes.com/showArticle.jhtml?articleID=181503693
Große, D., Drechsler, R.: Checkers for SystemC Designs. In: Proc. ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2004) (2004)
Habibi, A., Tahar, S.: Design and Verification of SystemC Transaction Level Models. IEEE Transactions on VLSI Systems 14(1) (January 2006)
Karlsson, D., Eles, P., Peng, Z.: Formal Verification of SystemC Designs Using a Petri-Net Based Representation. In: Proc. DATE 2006 (2006)
Klingauf, W., Burton, M., Günzel, R., Golze, U.: Why We Need Standards for Transaction-Level Modeling. SOC Central (April 2007)
Lahbib, Y., Perrin, A., Maillet-Contoz, L., Clouard, A., Ghenassia, F., Tourki, R.: Enriching the Boolean and the Modeling Layers of PSL with SystemC and TLM Flavors. In: Proc. FDL 2006 (2006)
Lahbib, Y.: Extension of Assertion-Based Verification Approaches for the Verification of SystemC SoC Models. PhD thesis, Univ. of Monastir, Tunisia (2006)
Lefftz, V., Bertrand, J., Cassé, H., Clienti, C., Coussy, P., Maillet-Contoz, L., Mercier, P., Moreau, P., Pierre, L., Vaumorin, E.: A Design Flow for Critical Embedded Systems. In: Proc. IEEE Symposium on Industrial Embedded Systems (SIES) (July 2010)
Jon Michelson and Faisal Haque. Assertions Improve Productivity for All Development Phases. EETimes (July 2007), http://www.eetimes.com/design/edadesign/4018491/Assertions-Improve-Productivity-for-All-Development-Phases
Moy, M., Maraninchi, F., Maillet-Contoz, L.: LusSy: an open tool for the analysis of systems-on-a-chip at the transaction level. Design Automation for Embedded Systems (2006)
Niemann, B., Haubelt, C.: Assertion-Based Verification of Transaction Level Models. In: Proc. ITG/GI/GMM Workshop (February 2006)
Oddos, Y., Morin-Allory, K., Borrione, D.: Assertion-Based Design with Horus. In: Proc. MEMOCODE 2008 (2008)
Pierre, L., Ferro, L.: A Tractable and Fast Method for Monitoring SystemC TLM Specifications. IEEE Transactions on Computers 57(10) (October 2008)
Pierre, L., Ferro, L.: Enhancing the Assertion-Based Verification of TLM Designs with Reentrancy. In: Proc. MEMOCODE 2010 (2010)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Ferro, L., Pierre, L., Bel Hadj Amor, Z., Lachaize, J., Lefftz, V. (2011). Runtime Verification of Typical Requirements for a Space Critical SoC Platform. In: Salaün, G., Schätz, B. (eds) Formal Methods for Industrial Critical Systems. FMICS 2011. Lecture Notes in Computer Science, vol 6959. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24431-5_4
Download citation
DOI: https://doi.org/10.1007/978-3-642-24431-5_4
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-24430-8
Online ISBN: 978-3-642-24431-5
eBook Packages: Computer ScienceComputer Science (R0)