Abstract
Efficient transaction nesting is one of the ongoing challenges for hardware transactional memory. To increase efficiency of closed nesting, this paper proposes a conditional partial rollback (CPR) scheme which supports conditional partial rollback without increasing hardware complexities significantly. In stead of rolling back to the outermost transaction as in commonly-used flattening model, the CPR scheme just rolls back to the conflicted transaction itself or one of its outer-level transactions if given conditions are satisfied. By recording access status of each nested transaction, the scheme uses one global data set for all of the nested transactions rather than independent data set for each nested transaction. Hardware transactional memory architecture with the support of CPR scheme is also proposed based on multi-core processor and current cache coherence mechanism. The system is implemented by simulation, and evaluated using seven benchmark applications. Evaluation results show that the CPR scheme achieves better performance and scalability than the flattening model which is commonly-used in hardware transactional memory.
This work is supported by National Science Foundation of China under grant No. 60873053 and National Hi-tech R&D Program (863 program) of China under grant No. 2009AA01Z107.
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Liu, Y. et al. (2010). Efficient Transaction Nesting in Hardware Transactional Memory. In: Müller-Schloer, C., Karl, W., Yehia, S. (eds) Architecture of Computing Systems - ARCS 2010. ARCS 2010. Lecture Notes in Computer Science, vol 5974. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11950-7_13
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DOI: https://doi.org/10.1007/978-3-642-11950-7_13
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