Abstract
There are many examples in the literature of applications that show different communication needs within a MPSoC. Very often cores interconnected through a Network-on-Chip have routers containing different buffers size, with different clock speed requirements. In this context, we are proposing a dynamic reconfigurable router for a NoC. With the proposed architecture it is possible to reconfigure the depth of each FIFO of the channel inside the routers. It allows more reusability in the NoC since the FIFO depth in the channels can be defined in accordance with the application. Besides, a buffer that is not used by its own channel can be used by others channel, reducing the power consumption.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Benini, L., De Micheli, G.: Network on Chips: A new SoC Paradigm. IEEE Computer, 70–78 (2002)
Manferdelli, J., Govindaraju, N., Crall, C.: Challenges and Opportunities in Many-Core Computing. Proceeding of the IEEE 96(5), 808–815 (2008)
Andrews, J., Baker, N.: Xbox 360 System Architecture. IEEE Micro 26(2), 25–37 (2006)
Cardoso, R., Kreutz, M., Carro, S., Susin, A.: Design Space Exploration on Heterogeneous Network-on-chip. In: International Symposium on Circuits and Systems, vol. 1, pp. 428–431 (2005)
Kreutz, M., Marcon, C., Carro, L., Wagner, F., Susin, A.: Design Space Exploration Comparing Homogenous and Heterogeneous Network-on-Chip Architectures. In: Symposium on Integrated Circuits and Systems Design, SBCCI 2005, pp. 190–195 (2005)
Ahmad, B., Ahmadinia, A., Arslan, T.: Dynamically Reconfigurable NOC with Bus Based Interface for Ease of Integration and Reduced Designed Time. In: NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2008), pp. 309–314 (2008)
Ahonen, T., Nurmi, J.: Hierarchically Heterogeneous Network-on-Chip. In: The International Conference on Computer as a Tool, EUROCON, pp. 2580–2586 (2007)
Eun Lee, S., Bagherzadeh, N.: Increasing the Throughput of an Adaptive Router in Network-on-Chip (NoC). In: International Conference on Hardware/ Software Codesign and System Synthesis, pp. 82–87 (2006)
Wu, C., Chi, H.: Design of a High-Performance Switch for Circuit-Switched On-Chip Networks. In: Asian Solid-State Circuits Conference, pp. 481–484 (2005)
Varatkar, G.V., Marculescu, R.: On-chip traffic modeling and synthesis for MPEG-2 video applications. IEEE Transactions on Very Large Scale Integration (VLSI) System, 108–119 (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Matos, D., Concatto, C., Carro, L., Kastensmidt, F., Susin, A. (2009). The Need for Reconfigurable Routers in Networks-on-Chip. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2009. Lecture Notes in Computer Science, vol 5453. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00641-8_28
Download citation
DOI: https://doi.org/10.1007/978-3-642-00641-8_28
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-00640-1
Online ISBN: 978-3-642-00641-8
eBook Packages: Computer ScienceComputer Science (R0)