Abstract
Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodology based on an evolutionary tool which exploits high level metrics is presented. To strengthen the correlation between high-level coverage and the gate-level fault coverage, in the case of peripheral cores, the FSMs embedded in the system are identified and then dynamically extracted via simulation, while transition coverage is used as a measure of how much the system is exercised. The results obtained by the evolutionary tool outperform those obtained by a skilled engineer on the same benchmark.
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Ravotto, D., Sanchez, E., Schillaci, M., Squillero, G. (2008). An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction. In: Giacobini, M., et al. Applications of Evolutionary Computing. EvoWorkshops 2008. Lecture Notes in Computer Science, vol 4974. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78761-7_22
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DOI: https://doi.org/10.1007/978-3-540-78761-7_22
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