Abstract
This paper presents a 32-bit floating-point CORDIC co- processor on FPGA, providing all known CORDIC functions. Firstly, we propose a hybrid-mode algorithm, combining hybrid rotation angle methods with argument reduction algorithm to reduce hardware area usage and meanwhile keep unlimited convergence domain for any floating-point inputs. And according to algorithm, the hybrid-mode CORDIC co-processor is organized into three phases, argument reduction, CORDIC calculation and normalization with 34 pipeline stages for FPGA implementation. The synthesis results show the clock frequency can reach 217MHz on Xilinx Virtex5 FPGA. Comparing to general-purpose microprocessor in three scientific program kernels, the CORDIC co-processor can guarantee at least 23-bit precision and achieve a maximum speedup of 47.6 times, 35.2 times in average.
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References
Andraks, R.: A survey of cordic algorithm for fpga based computers. In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, pp. 191–200 (1998)
Xiaobo, H., Ronald, G.H., Steven, C.B.: Expanding the range of convergence of the cordic algorithm. IEEE Transactions on Computers 40, 13–21 (1991)
Maharatna, K., Troya, A., Banerjee, S., Grass, E.: Virtually scaling-free adaptive cordic rotator. Computers and Digital Techniques, IEE Proceedings 151, 448–456 (2004)
Maharatna, K., Dhar, A.S., Banerjee, S.: A vlsi array architecture for realization of dft, dht, dct and dst. Signal Process 81, 1813–1822 (2001)
Ravichandran, S., Asari, V.: Implementation of unidirectional cordic algorithm using precomputed rotation bits. Circuits and Systems 3, 453–456 (2002)
Timmermann, D., Hahn, H., Hosticka, B.: Low latency time cordic algorithms. IEEE Trans. Computers 41, 1010–1015 (1992)
Vadlamani, S., Mahmoud, D.W.: Comparison of CORDIC Algorithm Implementations on FPGA Families. System Theory [e]. Tennessee Technol, Univ. USA (2002)
Valls, J., hlmann, M., Parhi, K.: Efficient mapping of cordic algorithm on fpga. In: Signal Processing Systems, pp. 336–345 (2000)
Volder, J.E.: The cordic trigonometric computing technique. IRE Trans. Electron. Comput. 8, 330–334 (1959)
Walther, J.S.: A unified algorithm for elementary functions. In: Proc. AFIPS Conf., vol. 38, pp. 389–395 (1971)
Hu, X., Bass, S.C., Harber, R.G.: An efficient implementation of singular value decomposition rotation transformations with cordic processor. J. Parallel Distrib. Comput. 17, 360–362 (1993)
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Zhou, J., Dou, Y., Lei, Y., Dong, Y. (2008). Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2008. Lecture Notes in Computer Science, vol 4943. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78610-8_25
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DOI: https://doi.org/10.1007/978-3-540-78610-8_25
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-78609-2
Online ISBN: 978-3-540-78610-8
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