Abstract
In this paper we present a new static power minimization technique exploiting the use of triple-threshold CMOS standard cell libraries in 90nm technology. Using static timing analysis, we determine the timing requirements of cells and place cells with low and standard threshold voltages in the critical paths. Cells with a high threshold voltage are placed in non-critical paths to minimize the static power with no overall timing degradation. From the timing and power analysis, we determine the optimal placement of high, standard and low threshold voltage cells. Using three different threshold voltages, an optimized triple-threshold 16-bit multiplier design featured 90% less static power compared to the pure low-threshold design and 54% less static power compared to the dual-threshold design.
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Kim, N.S., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J.S., Irwin, M.J., Kandemir, M., Narayanan, V.: Leakage current: Moore’s Law meets static power. IEEE Computer 36, 68–75 (2003)
Shin, K., Kim, T.: Leakage power minimization in arithmetic circuits. In: Electronics Letters, vol. 40, pp. 415–417. The Institution of Engineering and Technology (2004)
Chung, B., Kuo, J.B.: Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology. In: ISCAS, pp. 3650–3653 (2006)
Wei, L., Chen, Z., Roy, K., Johnson, M.C., Ye, Y., De, V.K.: Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. on VLSI Systems 7, 16–24 (1999)
Anis, M., Areibi, S., Elmasry, M.: Design and optimization of multithreshold CMOS (MTCMOS) circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 22, 1324–1342 (2003)
Srivastav, M., Rao, S.S.S.P., Bhatnagar, H.: Power reduction technique using multi-Vt libraries. In: System-on-Chip for Real-Time Applications, pp. 363–367. Springer, Heidelberg (2005)
Fujii, K., Douseki, T., Harada, M.: A sub-1 V triple-threshold CMOS/SIMOX circuit for active power reduction. In: ISSCC Digest of Technical Papers, pp. 190–191. S3 Digital Publishing Inc., Maine (1998)
Fujii, K., Douseki, T.: A 0.5-V, 3-mW, 54x54-b multiplier with a triple-Vth CMOS/SIMOX circuit scheme. In: IEEE International SOI Conference, pp. 73–74. IEEE, Los Alamitos (1999)
Chen, H.I.A., Loo, E.K.W, Kuo, J.B., Syrzycki, M.J.: Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology. In: Canadian Conference on Electrical and Computer Engineering, IEEE, Los Alamitos (2007)
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Chen, H.I.A., Loo, E.K.W., Kuo, J.B., Syrzycki, M.J. (2007). Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_44
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DOI: https://doi.org/10.1007/978-3-540-74442-9_44
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74441-2
Online ISBN: 978-3-540-74442-9
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