Keynote Multithreading for Low-Cost, Low-Power Applications

Abstract

Innovative architectural design may be the best route to create an economical and efficient balance between memory and logic elements in cost and power sensitive embedded solutions. When system prices are measured in a few euros instead of a few hundred, the large, power intensive and costly memory hierarchy solutions typically used in computer and communications applications are impractical. A multithreading extension to the microprocessor core is especially for deeply embedded systems a more effective approach.

Infineon has developed a new processor solution: TriCore 2. It is the second generation of the TriCore Unified Processor architecture. TriCore 2 contains, among others, a block multithreading solution, which responds to the blocking code memory latency in one thread by executing the instructions of a second thread. In this way, the execution pipelines of the processor can be almost fully utilized. From the user programming model, each thread can be seen as one virtual processor.

A typical scenario is a cell phone. Here, generally external 16-bit flash memories with a speed of 40 MHz are used while today’s performance requirements expect processors with a clock speed of 300-400 MHz. Because of this discrepancy, up to 80% of the performance can be lost, despite caches. Larger cache sizes and multi-level memory solutions are not applicable for cost reasons.

Block multithreading allows system designers to use comparatively smaller instruction caches and slow external memory while still getting the same overall performance. The performance degradation in the cell phone example can be almost eliminated. Even the clock frequency can be reduced. Block multithreading is very efficient for a general CPU based application residing in cache memory and an algorithmic application in the local on-chip memory. This is a characteristic which many deeply embedded processor applications have. Effectively, a separate DSP and CPU can be replaced by a multithreaded hybrid to reduce chip area, tool costs etc. The block multithreading solution also supports a fast interrupt response, required for most deeply embedded applications.

The additional costs for this multithreading solution are small. The implementation in TriCore 2 requires a chip area of only 0.3mm2 in 0.13 micron technology. The most obvious costs are caused by the duplicated register files to eliminate the penalty for task switching. Instruction cache and fetch unit need to support multithreading but the overhead is low. Same to other areas that are affected which are traps and interrupt handling, virtual memory, and debug/trace.

Apart from multithreading, TriCore 2 has also other highlights. Advanced pipeline technology allows high instruction per cycle (IPC) performance while reaching higher frequencies (400-600 MHz typical) and complying with demanding automotive requirements. The center of the processor’s hierarchical memory subsystem is an open, scalable crossbar architecture, which provides a method for efficient parallel communication to code and data memory including multiprocessor capability.

This presentation will describe the root problems in low-cost, low-power embedded systems that require a multithreaded processor solution.

Since the core architecture is well-deployed in the demanding automotive market, the first implementation is specified for these requirements like quality and determinism. Working silicon with this implementation is expected for the first quarter of 2004 and will be used as a demonstrator.