Skip to main content

Deadlock in Packet Switching Networks

  • Conference paper
  • First Online:
Fundamentals of Software Engineering (FSEN 2021)

Abstract

A deadlock in a packet switching network is a state in which one or more messages have not yet reached their target, yet cannot progress any further. We formalize three different notions of deadlock in the context of packet switching networks, to which we refer as global, local and weak deadlock. We establish the precise relations between these notions, and prove they characterize different sets of deadlocks. Moreover, we implement checking of deadlock freedom of packet switching networks using the symbolic model checker nuXmv. We show experimentally that the implementation is effective at finding subtle deadlock situations in packet switching networks.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 59.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 79.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    This is the same network as in Example 4, but with \(c_5 = 1\) instead of \(c_5 = \bot \).

References

  1. Benini, L., Micheli, G.D.: Networks on chips: a new SoC paradigm. Computer 35(1), 70–78 (2002). https://doi.org/10.1109/2.976921

    Article  Google Scholar 

  2. Cavada, R., et al.: The nuXmv symbolic model checker. In: Biere, A., Bloem, R. (eds.) CAV 2014. LNCS, vol. 8559, pp. 334–342. Springer, Cham (2014). https://doi.org/10.1007/978-3-319-08867-9_22

    Chapter  Google Scholar 

  3. Cavada, R., et al.: nuXmv 1.1.1 user manual. Technical report (2016)

    Google Scholar 

  4. Chen, R.C.: Deadlock prevention in message switched networks. In: Proceedings of the 1974 Annual Conference, vol. 1, p. 306–310. ACM, New York (1974). https://doi.org/10.1145/800182.810417

  5. Clarke, E.M., Emerson, E.A.: Design and synthesis of synchronization skeletons using branching time temporal logic. In: Kozen, D. (ed.) Logic of Programs 1981. LNCS, vol. 131, pp. 52–71. Springer, Heidelberg (1982). https://doi.org/10.1007/BFb0025774

    Chapter  Google Scholar 

  6. Coffman, E.G., Elphick, M.J., Shoshani, A.: Deadlock problems in computer system. In: Händler, W., Spies, P.P. (eds.) Rechnerstrukturen und Betriebsprogrammierung. LNCS, vol. 13, pp. 311–325. Springer, Heidelberg (1974). https://doi.org/10.1007/3-540-06815-5_147

    Chapter  Google Scholar 

  7. Dally, W.J., Towles, B.P.: Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., San Francisco (2004)

    Google Scholar 

  8. Duato, J.: A necessary and sufficient condition for deadlock-free routing in cut-through and store-and-forward networks. IEEE Trans. Parallel Distrib. Syst. 7(8), 841–854 (1996). https://doi.org/10.1109/71.532115

    Article  Google Scholar 

  9. López, P.: Routing (Including Deadlock Avoidance). Springer, Boston (2011). https://doi.org/10.1007/978-0-387-09766-4_314

    Book  Google Scholar 

  10. Merlin, P., Schweitzer, P.: Deadlock avoidance in store-and-forward networks - I: store-and-forward deadlock. IEEE Trans. Commun. 28(3), 345–354 (1980). https://doi.org/10.1109/TCOM.1980.1094666

    Article  MathSciNet  Google Scholar 

  11. Stramaglia, A., Keiren, J., Zantema, H.: Deadlocks in packet switching networks arXiv:2101.06015 [cs.NI] (2021). https://arxiv.org/abs/2101.06015

  12. Stramaglia, A.: Deadlock in packet switching networks. Master’s thesis, Università degli Studi di Trieste, Dipartimento di Ingegneria e Architettura, Trieste, Italy (2020)

    Google Scholar 

  13. Toueg, S., Ullman, J.D.: Deadlock-free packet switching networks. SIAM J. Comput. 10(3), 594–611 (1981). https://doi.org/10.1137/0210044

    Article  MathSciNet  MATH  Google Scholar 

  14. Verbeek, F.: Formal verification of on-chip communication fabrics. Ph.D. thesis, Radboud Universiteit Nijmegen (2013). https://hdl.handle.net/2066/103932

  15. Verbeek, F., Schmaltz, J.: Formal specification of networks-on-chips: deadlock and evacuation. In: 2010 Design, Automation Test in Europe Conference Exhibition (DATE 2010), pp. 1701–1706, March 2010. https://doi.org/10.1109/DATE.2010.5457089

  16. Verbeek, F., Schmaltz, J.: Formal validation of deadlock prevention in networks-on-chips. In: Proceedings of the Eighth International Workshop on the ACL2 Theorem Prover and Its Applications, ACL2 2009, pp. 128–138. ACM, New York, May 2009. https://doi.org/10.1145/1637837.1637858

  17. Wolfson, O.: A new characterization of distributed deadlock in databases. In: Ausiello, G., Atzeni, P. (eds.) ICDT 1986. LNCS, vol. 243, pp. 436–444. Springer, Heidelberg (1986). https://doi.org/10.1007/3-540-17187-8_52

    Chapter  Google Scholar 

  18. Zöbel, D.: The deadlock problem: a classifying bibliography. ACM SIGOPS Oper. Syst. Rev. 17(4), 6–15 (1983). https://doi.org/10.1145/850752.850753

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Anna Stramaglia .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2021 IFIP International Federation for Information Processing

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Stramaglia, A., Keiren, J.J.A., Zantema, H. (2021). Deadlock in Packet Switching Networks. In: Hojjat, H., Massink, M. (eds) Fundamentals of Software Engineering. FSEN 2021. Lecture Notes in Computer Science(), vol 12818. Springer, Cham. https://doi.org/10.1007/978-3-030-89247-0_9

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-89247-0_9

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-89246-3

  • Online ISBN: 978-3-030-89247-0

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics