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Application-Specific Routing Algorithms for Low Power Network on Chip Design

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Low Power Networks-on-Chip

Abstract

In the last few years, Network-on-Chip (NoC) has emerged as a dominant paradigm for synthesis of a multi-core Systems-on-Chip (SoC). A future NoC architecture must be general enough to allow volume production and must have features for specialization and configuration to match and meet the application’s power and performance requirements. This chapter describes how one important aspect, namely the routing algorithm, can be optimized in such NoC platforms. Routing algorithm has a major effect on the performance (packet latency and throughput) as well as power consumption of NoC. A methodology to develop efficient and deadlock free routing algorithms which are specialized for an application or a set of concurrent applications is presented. The methodology, called application-specific routing algorithms (APSRA), exploits the application-specific information regarding pairs of cores which communicate and other pairs which never communicate in the NoC platform. This information is used to maximize the adaptivity of the routing algorithm without compromising the important property of deadlock freedom. The chapter also presents an extensive comparison between the routing algorithms generated using APSRA methodology and general purpose deadlock-free routing algorithms. The simulation-based evaluations are performed using both synthetic traffic and traffic from real applications. The comparison embraces several performance indices such as degree of adaptiveness, average delay, throughput, power dissipation, and energy consumption. In spite of an adverse impact on router architecture, it is shown that the higher adaptivity of APSRA leads to significant improvements in both routing performance and energy consumption.

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Notes

  1. 1.

    A network is said to start saturating when increase in applied load does not result in linear increase in throughput [41].

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Authors and Affiliations

  1. Dipartimento di Ingegneria Informatica e delle Telecomunicazioni, University of Catania, Catania, Italy

    Maurizio Palesi

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  1. Maurizio Palesi
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  2. Rickard Holsmark
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  3. Shashi Kumar
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  4. Vincenzo Catania
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Correspondence to Maurizio Palesi .

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Editors and Affiliations

  1. Dipto. Elettronica e Informazione (DEI), Politecnico di Milano, Via Ponzio 34/5, Milano, 20133, Italy

    Cristina Silvano

  2. NEC Laboratories America, Inc., Independence Way 4, Princeton, 08540, New Jersey, USA

    Marcello Lajolo

  3. Dipto. Elettronica e Informazione (DEI), Politecnico di Milano, Via Ponzio 34/5, Milano, 20133, Italy

    Gianluca Palermo

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Palesi, M., Holsmark, R., Kumar, S., Catania, V. (2011). Application-Specific Routing Algorithms for Low Power Network on Chip Design. In: Silvano, C., Lajolo, M., Palermo, G. (eds) Low Power Networks-on-Chip. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6911-8_5

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  • DOI: https://doi.org/10.1007/978-1-4419-6911-8_5

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