Skip to main content
SpringerLink
Log in
Book cover

Processor and System-on-Chip Simulation pp 243–257Cite as

Thermal Modeling for Processors and Systems-on-Chip

  • Chapter
  • First Online:

  • 1878 Accesses

Abstract

Chip power density and consequently on-chip hot spot temperature have been increasing steadily as a result of non-ideal technology scaling, leading to severely thermally constrained designs. In this chapter, we review a chip- and package-level thermal modeling and simulation approach, HotSpot, that is unique because it is compact, correct by construction, flexible, and parameterized. HotSpot is important for temperature-aware design, especially during early pre-RTL stages of SoC and processor designs. Several case studies further illustrate the necessity of thermal simulations and the usefulness of HotSpot.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Notes

  1. 1.

    http://www.chipestimate.com/

References

  1. Huang, W., Stan, M.R., Skadron, K., Sankaranarayanan, K., Ghosh, S., Velusamy, S.: Compact thermal modeling for temperature-aware design. In: Proceedings of Design Automation Conference (DAC), pp. 878–883, June (2004).

    Google Scholar 

  2. Sabry, M.-N.: Compact thermal models for electronic systems. IEEE Trans Components Packaging Technol 26(1), 179–185, March (2003).

    Article  Google Scholar 

  3. Rosten, H.I., Lasance, C.J.M., Parry, J.D.: The world of thermal charaterization according to DELPHI–-part I: Background to DELPHI. IEEE Trans Components Packaging Technol 20(4), 384–391, December (1997).

    Article  Google Scholar 

  4. Lasance, C.J.M., Rosten, H.I., Parry, J.D.: The world of thermal charaterization according to DELPHI–-part II: Experimental and numerical methods. IEEE Trans Components Packaging Technol 20(4), 392–398, December (1997).

    Article  Google Scholar 

  5. Lasance, C.J.M.: The influence of various common assumptions on the boundary-condition-independence of compact thermal models. IEEE Trans Components, Packaging, Manufacturing Technol–Part A 27(3), 523–529, September (2004).

    Article  Google Scholar 

  6. Vinke, H., Lasance, C.J.M.: Compact models for accurate thermal charaterization of electronic parts. IEEE Trans Components, Packaging, Manufacturing Technol–Part A 20(4), 411–419, December (1997).

    Article  Google Scholar 

  7. Rosten, H., Lasance, C.: Delphi: The development of libraries of physical models of electronic components for an integrated design environment. In: Proceedings on Conference of International Electronics Packaging Society (CIEPS), (1994).

    Google Scholar 

  8. Bar-Cohen, A., Elperin, T., Eliasi, R.: \(\theta_{jc}\) charaterization of chip packages–-justification, limitations and future. IEEE Trans Components, Hybrids, Manufacturing Technol 12, 724–731, December (1989).

    Article  Google Scholar 

  9. Huang, W., Skadron, K., Sankaranarayanan, K., Ribando, R.J., Stan, M.R.: Accurate, pre-RTL temperature-aware processor design using a parameterized, Geometric thermal model. IEEE Trans Comput 57(9), 1277–1288, September (2008).

    Article  MathSciNet  Google Scholar 

  10. Huang, W., Humenay, E., Skadron, K., Stan, M.: The need for a full-chip and package thermal model for thermally optimized IC designs. In: Proceedings of the International Symposium on Low Power Electronic Design (ISLPED), pp. 245–250, August (2005).

    Google Scholar 

  11. Huang, W., Stan, M., Sankaranarayanan, K., Ribando, R., Skadron, K.: Many-core design from a thermal perspective. In: Proceedings of DAC, (2008).

    Google Scholar 

  12. Huang, W., Stan, M.R., Skadron, K., Ghosh, S., Velusamy, S., Sankaranarayanan, K.: Hotspot: A compact thermal modeling methodology for early-stage vlsi design. IEEE Trans Very Large Scale Integration (VLSI) Syst 14(5):501–513, May (2006).

    Article  Google Scholar 

  13. Huang, W., Stan, M.R., Skadron, K.: Parameterized physical compact thermal modeling. IEEE Trans Components Packaging Technol 28(4), 615–622, December (2005).

    Article  Google Scholar 

  14. Skadron, K., Stan, M.R., Huang, W., Velusamy, S., Sankaranarayanan, K., Tarjan, D.: Temperature-aware microarchitecture. In: Proceedings of the International Symposium on Computer Architecture (ISCA), pp. 2–13, June (2003).

    Google Scholar 

  15. Parry, J., Rosten, H., Kromann, G.B.: The development of component-level thermal compact models of a C4/CBGA interconnect technology: The motorola PowerPC 603 and PowerPC 604 RISC microproceesors. IEEE Trans Components Packaging Manufacturing Technol–Part A 21(1), 104–112, March (1998).

    Article  Google Scholar 

  16. Huang, W., Skadron, K., Gurumurthi, S., Ribando, R.J., Stan, M.R.: Differentiating the roles of IR measurement and simulation for power and temperature-aware design. In: Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April (2009).

    Google Scholar 

  17. Velusamy, S., Huang, W., Lach, J., Stan, M.R., Skadron, K.: Monitoring temperature in fpga based socs. In: Proceedings of the International Conference on Computer Design (ICCD), pp. 634–637, October 2005.

    Google Scholar 

  18. Stolberg, H., Moch, S., Friebe, L., Dehnhardt, A., Kulaczewski, M., Berekovic, M., Pirsch, P.: An soc with two multimedia dsps and a risc core for video compression applications. In: Digest of Papers, IEEE International Solid-State Circuits Conference (ISSCC), February (2004).

    Google Scholar 

  19. The International Technology Roadmap for Semiconductors (ITRS), (2007).

    Google Scholar 

  20. Heo, S., Barr, K., Asanovic, K.: Reducing power density through activity migration. In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 217–222, August (2003).

    Google Scholar 

  21. Srinivasan, J., Adve, S.V., Bose, P., Rivers, J.A.: The impact of technology scaling on lifetime reliability. In: Proceedings of the International Conference on Dependable Systems and Networks (DSN), June (2004).

    Google Scholar 

  22. Skadron, K., Sankaranarayanan, K., Velusamy, S., Tarjan, D., Stan, M.R., Huang, W.: Temperature-aware microarchitecture: Modeling and implementation. ACM Trans Arch Code Optim 1(1), 94–125, March (2004).

    Article  Google Scholar 

  23. Sankaranarayanan, K., Velusamy, S., Stan, M.R., Skadron, K.: A case for thermal-aware floorplanning at the microarchitectural level. J Instr-Level Parallelism 7, October (2005).

    Google Scholar 

  24. Lasance, C.J.M.: The urgent need for widely-accepted test methods for thermal interface materials. In: Proceedings of the 19th IEEE SEMI-THERM Symposium, pp. 123–128, (2003).

    Google Scholar 

  25. Han, Y., Koren, I., Moritz, C.A.: Temperature-aware floorplanning. In: Proceedings of Workshop on Temperature-Aware Computer Systems (TACS), (2005).

    Google Scholar 

  26. Li, Y., Lee, B., Brooks, D., Hu, Z., Skadron, K.: CMP design space exploration subject to physical constraints. In: Proceedings of HPCA, (2006).

    Google Scholar 

  27. Chaparro, P., Gonzalez, J., Magklis, G., Cai, Q., Gonzalez, A.: Understanding the thermal implications of multicore architectures. IEEE Trans Parallel Distributed Syst 18(8), 1055–1065, (2007).

    Article  Google Scholar 

  28. Memik, S.O., Mukherjee, R., Ni, M., Long, J.: Optimizing thermal sensor allocation for microprocessors. IEEE Trans Comput Aided Design 27(3), 516–527, March (2008).

    Article  Google Scholar 

  29. Sharifi, S., Simunic Rosing, T.: Accurate temperature sensing for efficient thermal management. In: Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), (2008).

    Google Scholar 

  30. Memik, S.O., Mukherjee, R.: An integrated approach to thermal management in high-level synthesis. IEEE Trans VLSI 14(11), 1165–1174, November (2006).

    Article  Google Scholar 

  31. Yang, S., Wolf, W., Vijaykrishnan, N., Xie, Y.: Reliability-aware SOC voltage islands partition and floorplan. In: Proceedings of IEEE Annual Symposium on VLSI (ISVLSI), (2006).

    Google Scholar 

  32. He, Z., Peng, Z., Eles, P., Rosinger, P., Al-Hashimi, B.M.: Thermal-aware SoC test scheduling with test set partitioning and interleaving. J Electron Testing Theory Appl 24(1–3), 247–257, (2008).

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science, University of Virginia, Charlottesville, VA, 22904, USA

    Kevin Skadron

  2. University of Virginia, Charlottesville, VA, USA

    Mircea Stan

  3. IBM Research, Austin, TX, USA

    Wei Huang

Authors
  1. Kevin Skadron
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Mircea Stan
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Wei Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Kevin Skadron .

Editor information

Editors and Affiliations

  1. RWTH Aachen University, Templergraben 55, Aachen, 52056, Germany

    Rainer Leupers

  2. INRIA Futurs, rue Jean Monod 4, Orsay CX, 91893, France

    Olivier Temam

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer Science+business Media, LLC

About this chapter

Cite this chapter

Skadron, K., Stan, M., Huang, W. (2010). Thermal Modeling for Processors and Systems-on-Chip. In: Leupers, R., Temam, O. (eds) Processor and System-on-Chip Simulation. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6175-4_15

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-6175-4_15

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-6174-7

  • Online ISBN: 978-1-4419-6175-4

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation