Skip to main content

Substrate Technology

  • Chapter
  • First Online:
Advanced Flip Chip Packaging

Abstract

A flip chip package started with a ceramic substrate at the beginning. A Low CTE chip (silicon: 3ppm/°C) and a relatively low CTE substrate (alumina: 8ppm/°C) with a ductile solder joint (high lead solder) provided a good reliable system for high density packaging. However, it has disadvantages such as high cost, low electrical property, largeness, and heaviness. In early 1990s, an organic substrate utilizing an epoxy base printed circuit board technology has emerged. An underfill resin fills a gap between a chip and substrate and resolves a stress issue by a large CTE mismatch of a chip and an organic substrate (17ppm/°C). In this system, the stress at a flip chip joint is dispersed in to the total package entity. This technology opened a door to low cost, high electrical property, small and light package, and has spread throughout semiconductor packages. In this chapter, a major focus is put on the organic substrate technology. The material, process, and reliability influences to a package are described in detail. Particularly, it is emphasized that the basics why the organic substrate is designed in such a way as we see today. Though there are many variations in the organic substrate technology, the basics are common and very important for a productive and reliable package, and the future progress of a flip chip package is strongly dependent on the progress of such basics.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 139.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 179.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 219.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Tummala R, Rymaszewski E (eds) (1989) Microelectronics packaging handbook. Van Nostrand Rheinhold, New York

    Google Scholar 

  2. Tsukada Y (1991) Low cost multi-layer thin film substrate, filling a gap to semiconductor. Nikkei Micro Device 73:61–67

    Google Scholar 

  3. Tsukada Y, Mashimoto Y, Nishio T, Mii N (1992) Reliability and stress analysis of encapsulated flip chip joint on epoxy base printed circuit board. In: Proceedings of ASEM/JSME joint conference for advanced in electronics packaging-milpitas CA, vol 2, pp 827–835

    Google Scholar 

  4. Tsukada Y, Tsuchida S, Mashimoto Y (1992) Surface laminar circuit packaging. In: Proceeding of IEEE 42nd electronics components & technology conference, San Diego, CA, pp 22–27

    Google Scholar 

  5. Tsukada Y, Yamanaka K, Kodama Y, Kobayashi K (2002) Features of new laser micro-via organic substrate for semiconductor package. In: Proceeding of ISE 27th international electronics manufacturing technology conference, Dusseldorf

    Google Scholar 

  6. Tsukada Y (1998) Introduction of build-up PCB technology. Nikkan kogyo newspaper publication

    Google Scholar 

  7. Watanabe K, Fujimura T, Nishiwaki T, Tashiro K, Honma H (2004) Surface modification of insulation resin for build-up process using TiO2 as a photo catalist and its application to the metallization. J JIEP 7(2):136–140

    Google Scholar 

  8. Tsukada Y, Kido Y (2011) Bonding of heterogeneous material using molecular interface technology, application to organic substrate. Electronics Packaging Technol, 27(1)

    Google Scholar 

  9. Toda K (2011) Anisotropic etching for ultra fine pitch pattern formation using a subtractive method. In: 12th PWB EXPO technical conference, Tokyo

    Google Scholar 

  10. Mago G (2011) Text of technical seminar. 40th Iinter NEPCON Japan, Tokyo

    Google Scholar 

  11. Nishiki S (2009) Advanced copper plating wiring technology. CMC Publication, pp 198–207

    Google Scholar 

  12. Tsukada Y (2008) Issues on flip chip bonding technology and future direction. In: Presentation at 4th JIEP-west technical lecture, Osaka

    Google Scholar 

  13. Tsukada Y (2005) The packaging, 10 years from now. Presentation at JIEP International Conference of Electronics Packaging, Tokyo

    Google Scholar 

  14. Tsukada Y (2000) High density, high performance and low cost flip chip technology. Nikkan kogyo newspaper publication

    Google Scholar 

  15. Orii Y (2011) C4NP solder bump build technology. In: 481st Technical seminar, electric Journal, Tokyo

    Google Scholar 

  16. Nishio T (2008) In: Text of technical seminar, 37th Iinter NEPCON Japan, Tokyo

    Google Scholar 

  17. Goldman L (1969) Geometric optimization of controlled collapse interconnections. IBM J Res Dev 13:251–265

    Article  Google Scholar 

  18. Tsukada Y (2004) A consideration for total mechanical stress in flip chip packaging utilizing build up substrate technology. In: Presentation at TC6, IEEE 54th electronics component and technology conference, Las Vegas

    Google Scholar 

  19. Sasaoka K, Yoshimura H, Takeuchi K, Terauchi T, Tsuchiko M (2010) Development of new buildup PWB with embedded both active devices and chip passive components at the same time. In: Proceedings of 16th symposium on microjoining and assembly technology in electronics, pp 369–374

    Google Scholar 

  20. Sasaoka K, Motomura T, Morioka N, Fukuoka Y (2007) Development of substrate with embedded bare chip and passives. In: Proceedings of 17th micro electronics symposium, pp 159–162

    Google Scholar 

  21. MaCbride R, Rosser S, Nowak R (2003) Modeling and simulation of 12.5Gb/s on a HyperBGA package. In: Proceedings of 28th IEMT symposium, IEEE

    Google Scholar 

  22. (2011) Nikkei Electronics, 5–2(1055):61–68 and pp 87–95

    Google Scholar 

  23. Baron D (2011) A Comprehensive packaging solution for advanced IC substrates using novel composite materials. In: Text of technical seminar, 40th Iinter NEPCON Japan, Tokyo

    Google Scholar 

  24. Yamanaka K, Kobayashi K, Hayashi K, and Fului M (2009) Advanced surface laminar circuit packaging with low coefficient of thermal expansion and high wiring density. In: Proceedings of 59th ECTC, IEEE, pp 325–332

    Google Scholar 

  25. Sakuma K, Sueoka K, Kohara S, Matsumoto K, Noma H, Aoki T, Oyama Y, Nishiwaki H, Andry P, Tsang C, Knickerbocker J, and Orii Y (2010) IMC bonding for 3D interconnection. In: Proceedings of 59th ECTC, IEEE, pp 864–871

    Google Scholar 

  26. Nakagawa S, Taira Y, Numata H, Kobayashi K, Terada K, Tsukada Y (2008) High-density optical interconnect exploiting build-up waveguide-on-SLC board. In: Proceedings of 58th ECTC, IEEE, pp 256–260

    Google Scholar 

  27. Tokunari M, Tsukada Y, Toriyama K, Noma H, Nakagawa S (2011) High-bandwidth density optical I/O for high-speed logic chip on waveguide-integrated organic carrier. Proceedings of 60th ECTC, IEEE, pp 819–822

    Google Scholar 

  28. Japan Packaging Roadmap, JEITA (2011)

    Google Scholar 

  29. ITRS roadmap, WEB

    Google Scholar 

Download references

Acknowledgment

The author thanks all firms and individuals who offered technical information and acceptance for its usage in this chapter.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Yutaka Tsukada .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer Science+Business Media New York

About this chapter

Cite this chapter

Tsukada, Y. (2013). Substrate Technology. In: Tong, HM., Lai, YS., Wong, C. (eds) Advanced Flip Chip Packaging. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-5768-9_7

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-5768-9_7

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5767-2

  • Online ISBN: 978-1-4419-5768-9

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics