Abstract
This paper presents the concept of reconfigurable systems using the example of a digital hardware implementation of neural networks, as well as RENCO, a platform very well-suited for the prototyping of such systems. RENCO is a network computer containing a reconfigurable part composed of four Flex10K FPGAs from Altera (10K130 or 1OK250).
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
References
Z. Salcic, A. Smailagic. Digital System Design and Prototyping Using Field Programmable Logic. Kluwer Academic Publishers, Boston, 1997.
E. Sanchez. Field Programmable Gate Array (FPGA) Circuits. In E. Sanchez, M. Tomassini (eds.). Towards Evolvable Hardware. Springer-Verlag, Berlin, 1997, pp. 1–18.
J. Villasenor, W. H. Mangione-Smith. Configurable Computing. Scientific American, June 1997, pp. 54–59.
M. Slater. The Many Faces of Network Computers. Microprocessor Report, Vol. 10, num. 16, 1996, p. 3.
Motorola. MC68360, Quad Integrated Communications Controller, User's Manual. 1993.
Altera Corporation. EPF10K130, Embedded Programmable Logic Device. San Jose, April 1997.
RTEMS Home Page, http://Lancelot.gcs.redstone.army.mil/rterns.html.
Kaffe, A free virtual machine to run Java(tm) code, http://www.kaffe.org/.
M. A. Lehr, B. Widrow. 30 Years of Adaptative Neural Networks: Perceptron, Madaline and Backpropagation. Proc. IEEE, 78(9): 1425–1442, September 1990.
S. Sakaue, T. Kohda, H. Yamamoto, S. Maruno, Y. Shimeki. Reduction of Required Bits for Backpropagation Applied to Pattern Recognition. IEEE Transactions on Neural Networks, Vol. 4, no. 2, March 1993, pp. 270–275.
J.G. Eldredge and B.L. Hutchings. Density Enhancement of a Neural Network Using FPGAs and Run-Time Reconfiguration. In Duncan A. Buell and Kenneth L. Pocek, editors, Proceedings of the IEEE Workshop on FPGAS for Custom Comput ing Machines, pages 180–188, Los Alamitos, California, April 1994. IEEE Computer Society, IEEE Computer Society Press.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1998 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Beuchat, JL., Haenni, JO., Sanchez, E. (1998). Hardware reconfigurable neural networks. In: Rolim, J. (eds) Parallel and Distributed Processing. IPPS 1998. Lecture Notes in Computer Science, vol 1388. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-64359-1_679
Download citation
DOI: https://doi.org/10.1007/3-540-64359-1_679
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-64359-3
Online ISBN: 978-3-540-69756-5
eBook Packages: Springer Book Archive